VDD Low Skew, 1:6 Crystal-to-LVCMOS/ 83905 LVTTL Fanout Buffer Datasheet General Description Features The 83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer. Six LVCMOS / LVTTL outputs The low impedance LVCMOS/LVTTL outputs are designed to Outputs able to drive 12 series terminated lines drive 50 series or parallel terminated transmission lines. The Crystal Oscillator Interface effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. Crystal input frequency range: 10MHz to 40MHz The 83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed Output skew: 80ps (maximum) 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply RMS phase jitter 25MHz, (100Hz 1MHz): 0.26ps (typical), mode. Guaranteed output and part-to-part skew characteristics V = V = 2.5V DD DDO along with the 1.8V output capabilities makes the 83905 ideal for Offset Noise Power high performance, single ended applications that also require a 100Hz.................-129.7 dBc/Hz limited output voltage. 1kHz...................-144.4 dBc/Hz 10kHz.................-147.3 dBc/Hz 100kHz...............-157.3 dBc/Hz 5V tolerant enable inputs Synchronous output enables Operating power supply modes: Full 3.3V, 2.5V, 1.8V Mixed 3.3V core/2.5V output operating supply Mixed 3.3V core/1.8V output operating supply Mixed 2.5V core/1.8V output operating supply 0C to 70C ambient operating temperature Lead-free (RoHS 6) packaging Pin Assignments 20 18 17 16 19 83905 GND 1 15 BCLK5 20-Lead VFQFN GND 2 14 VDDO 4mm x 4mm x 0.925mm Block Diagram BCLK0 3 13 BCLK4 package body VDDO 4 GND 12 K Package BCLK0 GND BCLK1 5 11 Top View 6 7 8 9 10 BCLK1 XTAL IN 83905 BCLK2 XTAL OUT 16-Lead SOIC, 150 Mil XTAL OUT 1 16 XTAL IN 3.9mm x 9.9mm x 1.38mm ENABLE2 2 15 ENABLE1 GND 3 14 BCLK5 package body BCLK3 BCLK0 13 4 VDDO M Package 5 12 V BCLK4 DDO Top View 11 BCLK1 6 GND BCLK4 GND 7 10 BCLK3 BCLK2 8 9 16-Lead TSSOP ENABLE 1 SYNCHRONIZE 4.4mm x 5.0mm x 0.925mm BCLK5 package body G Package ENABLE 2 SYNCHRONIZE Top View 2016 Integrated Device Technology, Inc. 1 Revision D September 27, 2016 GND ENABLE2 GND XTAL OUT BCLK2 XTAL IN VDD ENABLE1 BCLK3 nc83905 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Name Type Description XTAL OUT Output Crystal oscillator interface. XTAL OUT is the output. XTAL IN Input Crystal oscillator interface. XTAL IN is the input. ENABLE1, ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. BCLK0, BCLK1, BCLK2, Output Clock outputs. LVCMOS/LVTTL interface levels. BCLK3, BCLK4, BCLK5 GND Power Power supply ground. V Power Power supply pin. DD V Power Output supply pin. DDO nc Unused No connect. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN V = 3.465V 19 pF DDO Power Dissipation C Capacitance V = 2.625V 18 pF PD DDO (per output) = 2.0V 16 pF V DDO V = 3.3V 5% 7 DDO R Output Impedance V = 2.5V 5% 7 OUT DDO = 1.8V 0.2V 10 V DDO Function Table Table 3. Clock Enable Function Table Control Inputs Outputs ENABLE 1 ENABLE2 BCLK 0:4 BCLK5 0 0 LOW LOW 0 1 LOW Toggling 1 0 Toggling LOW 1 1 Toggling Toggling BCLK5 BCLK 0:4 ENABLE2 ENABLE1 Figure 1. Enable Timing Diagram 2016 Integrated Device Technology, Inc. 2 Revision D September 27, 2016