GND Q5 Q4 Q3 VDDO Q2 Q1 Q0 Low Skew, 1:18 83918 Crystal-to-LVCMOS/LVTTL Fanout Buffer Data Sheet General Description Features The 83918 is a low skew, 1:18 Crystal-to- LVCMOS/LVTTL Fanout Eighteen LVCMOS/LVTTL output Buffer. The 83918 has selectable LVCMOS/LVTTL clock or crystal Selectable crystal oscillator interface or LVCMOS CLK inputs. The low impedance LVCMOS/LVTTL outputs are designed to Maximum output frequency: 200MHz drive 50 series or parallel terminated transmission lines. Crystal input frequency range: 10MHz to 40MHz The 83918 is characterized at full 3.3V, full 2.5V and mixed RMS phase jitter using a 25MHz crystal (1kHz 1MHz): 0.449ps 3.3V/2.5V, 3.3V/1.8V, and 2.5V/1.8V output operating supply modes. (typical) 3.3V/3.3V Guaranteed output and part-to-part skew characteristics make the Output skew: 75ps (maximum) 3.3V/3.3V 83918 ideal for those clock distribution applications demanding well defined performance and repeatability. Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown CLK SEL XTAL IN 32 31 30 29 28 27 26 25 OSC 0 GND 1 24 Q6 XTAL OUT 18 Q0:Q17 GND 2 23 Q7 LVCMOS CLK 3 22 Q8 Pulldown LVCMOS CLK 1 CLK SEL 4 21 VDDO XTAL IN 5 20 Q9 XTAL OUT 6 19 Q10 VDD 7 18 Q11 VDDO 8 17 GND 9 10 11 12 13 14 15 16 83918 32 Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 2016 Integrated Device Technology, Inc 1 Revision B March 17, 2016 Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO83918 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Clock select pin. When HIGH, selects LVCMOS CLK. When LOW, 4 CLK SEL Input Pulldown selects crystal inputs. LVCMOS/LVTTL interface levels. 5, XTAL IN, Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the Input 6 XTAL OUT output. 7V Power Positive supply pin. DD 8, 16, 21, 29 V Power Output supply pins. DDO 9, 10, 11, Q17, Q16, Q15, 13, 14, 15, Q14, Q13, Q12, 18, 19, 20, 22, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. Q11, Q10, Q9, Q8, 23, 24, 26, 27, Q7, Q6, Q5, Q4, 28, 30, 31, 32 Q3, Q2,Q1, Q0 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN V = 3.465V 9 pF DDO Power Dissipation Capacitance C V = 2.625V 8 pF PD DDO (per output) V = 2V 8 pF DDO R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 18 19 20 DDO R Output Impedance V = 2.625V 20 22 24 OUT DDO V = 2V 25 29 34 DDO 2016 Integrated Device Technology, Inc 2 Revision B March 17, 2016