GND VDDO Q5 Q12 Q4 Q13 Q3 Q14 VDDO GND Q2 Q15 Q1 Q16 Q0 Q17 Low Skew, 1-to-18 83940-01 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer DATASHEET FEATURES GENERAL DESCRIPTION Eighteen LVCMOS/LVTTL outputs, 23 typical output impedance The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The Selectable LVCMOS CLK or LVPECL clock inputs PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels. The single ended clock input accepts LVCMOS or LVTTL input levels. The low LVCMOS CLK supports the following input types: impedance LVCMOS/LVTTL outputs are designed LVCMOS or LVTTL to drive 50 series or parallel terminated transmis- PCLK, nPCLK supports the following input types: sion lines. The effective fanout can be increased from 18 to LVPECL, CML, SSTL 36 by utilizing the ability of the outputs to drive two series terminated lines. Maximum output frequency: 250MHz The ICS83940-01 is characterized at full 3.3V, full 2.5V Output skew: 85ps (maximum) and mixed 3.3V input and 2.5V output operat- Part-to-part skew: 750ps (maximum) ing supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940-01 ideal for those clock Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes distribution applications demanding well defined 0C to 70C ambient operating temperature performance and repeatability. Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 Q6 GND 1 24 CLK SEL Q7 GND 2 23 Q8 PCLK LVCMOS CLK 3 22 0 nPCLK 18 VDDO CLK SEL 4 21 Q0:Q17 ICS83940-01 Q9 1 PCLK 5 20 LVCMOS CLK Q10 nPCLK 6 19 Q11 VDD 7 18 GND VDDO 17 8 9 10 11 12 13 14 15 16 32-Lead LQFP Y Pacakge 7mm x 7mm x 1.4mm package body Top View 83940-01 REVISION A NOVEMBER 4, 2014 1 2014 Integrated Device Technology, Inc.83940-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS CLK Input Pulldown Clock input. LVCMOS / LVTTL interface levels. Clock select input. Selects LVCMOS / LVTTL clock 4 CLK SEL Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs when LOW. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. 6 nPCLK Input V /2 default when left oating. DD 7V Power Power supply pin. DD 8, 16, 21, 29 V Power Output supply pins. DDO 9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13, 15, 18, 19, 20, 22, Q12, Q11, Q10, Q9, Q8, Output Clock outputs. LVCMOS / LVTTL interface levels. 23, 24, 26, 27, 28, Q7, Q6, Q5, Q4, Q3, 30, 31, 32 Q2, Q1, Q0 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Power Dissipation Capacitance C 6pF PD (per output) R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 18 28 OUT TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK SEL PCLK, nPCLK LVCMOS CLK 0 Selected De-selected 1 De-selected Selected TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity CLK SEL LVCMOS CLK PCLK nPCLK Q0:Q17 0 0 1 LOW Differential to Single Ended Non Inverting 0 1 0 HIGH Differential to Single Ended Non Inverting Biased 0 0 LOW Single Ended to Single Ended Non Inverting NOTE 1 Biased 0 1 HIGH Single Ended to Single Ended Non Inverting NOTE 1 0 Biased NOTE 1 0 HIGH Single Ended to Single Ended Inverting 0 Biased NOTE 1 1 LOW Single Ended to Single Ended Inverting 1 0 LOW Single Ended to Single Ended Non Inverting 1 1 HIGH Single Ended to Single Ended Non Inverting NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single Ended Levels. LOW SKEW, 1-TO-18 2 REVISION A 11/4/14 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER