GND Q5 Q4 Q3 VDDO Q2 Q1 Q0 Low Skew, 1 to 18 LVPECL to ICS83940DI Datasheet LVCMOS/LVTTL Fanout Buffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (83940DKILF) General Description Features The ICS83940DI is a low skew, 1 to 18 LVPECL to Eighteen LVCMOS/LVTTL outputs LVCMOS/LVTTL fanout buffer. The ICS83940DI has two Selectable LVCMOS CLK or LVPECL clock inputs selectable clock inputs. The PCLK, nPCLK pair can accept PCLK, nPCLK pair can accept the following differential input LVPECL, CML, or SSTL input levels. The LVCMOS CLK can levels: LVPECL, CML, SSTL accept LVCMOS or LVTTL input levels. The low impedance LVCMOS CLK supports the following input types: LVCMOS or LVCMOS/LVTTL outputs are designed to drive 50 series or LVTTL parallel terminated transmission lines. Maximum output frequency: 250MHz The ICS83940DI is characterized at full 3.3V and 2.5V or mixed Output skew: 150ps (maximum) 3.3V core, 2.5V output operating supply modes. Guaranteed Part-to-part skew: 750ps (maximum) output and part-to-part skew characteristics make the ICS83940DI ideal for those clock distribution applications demanding well Operating supply modes: defined performance and repeatability. Core/Output 3.3V/3.3V 3.3V/2.5V Block Diagram 2.5V/2.5V Pulldown CLK SEL -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Pulldown PCLK 0 Pullup/Pulldown For functional replacement part for 83940DKILF, use 87016i nPCLK 18 Q0:Q17 Pulldown LVCMOS CLK 1 Pin Assignments 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 GND 1 Q6 24 GND 1 24 Q6 GND 2 23 Q7 GND 2 23 Q7 LVCMOS CLK 3 22 Q8 LVCMOS CLK 3 22 Q8 CLK SEL 4 21 VDD CLK SEL 4 21 VDD ICS83940DI ICS83940DI PCLK 5 Q9 20 PCLK 5 20 Q9 nPCLK 6 Q10 nPCLK 6 19 19 Q10 VDD 7 18 Q11 VDD 7 Q11 18 VDDO 8 17 GND VDDO 8 GND 17 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 32 Lead VFQFN 32-Lead LQFP 5mm x 5mm x 0.925mm package body 7mm x 7mm x 1.4mm package body Y Package K Package Top View Top View 2020 Renesas Electronics Corporation 1 January 7, 2020 Q17 Q0 Q16 Q1 Q15 Q2 VDDO GND Q14 Q3 Q13 Q4 Q12 Q5 VDDO GND Q17 Q16 Q15 GND Q14 Q13 Q12 VDDOICS83940DI Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects LVCMOS CLK input. 4 CLK SEL Input Pulldown When LOW, selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ Inverting differential LVPECL clock input. V /2 default when left DD 6nPCLK Input Pulldown floating. 7, 21 V Power Power supply pin. DD 8, 16, 29 V Power Output supply pins. DDO 9, 10, 11, Q17, Q16, Q15, 13, 14, 15, Q14, Q13, Q12, 18, 19, 20, Q11, Q10, Q9, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 22, 23, 24, Q8, Q7, Q6, 26, 27, 28, Q5, Q4, Q3, 30, 31, 32 Q2, Q1, Q0 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Power Dissipation Capacitance C 6pF PD (per output) R Output Impedance 18 28 OUT 2020 Renesas Electronics Corporation 2 January 7, 2020