GND VDDO Q5 Q12 Q4 Q13 Q3 Q14 VDDO GND Q2 Q15 Q1 Q16 Q0 Q17 Low Skew, 1-to-18 83940D LVPECL-TO-LVCMOS / LVTTL Fanout Buffer DATASHEET GENERAL DESCRIPTION FEATURES The 83940D is a low skew, 1-to-18 LVPECL-to-LVC- 18 LVCMOS/LVTTL outputs MOS/LVTTL Fanout Buffer. The 83940D has two select- Selectable LVCMOS CLK or LVPECL clock inputs able clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS PCLK, nPCLK supports the following input types: CLK can accept LVCMOS or LVTTL input levels. The low LVPECL, CML, SSTL impedance LVCMOS/LVTTL outputs are designed to drive 50 LVCMOS CLK accepts the following input levels: series or parallel terminated transmission lines. LVCMOS or LVTTL The 83940D is characterized at full 3.3V and 2.5V or Maximum output frequency: 250MHz mixed3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make Output skew: 150ps (maximum) the 83940D ideal for those clock distribution applications Part to part skew: 750ps (maximum) demanding well de ned performance and repeatability. Additive phase jitter, RMS: < 0.03ps (typical) Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output supply modes 0C to 70C ambient operating temperature Lead-Free package available BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 GND 1 24 Q6 GND 2 23 Q7 LVCMOS CLK 3 22 Q8 CLK SEL 4 21 VDD ICS83940D PCLK 5 20 Q9 nPCLK 6 19 Q10 VDD 7 18 Q11 VDDO 17 GND 8 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Pacakge Top View 83940D REVISION B 3/25/15 1 2015 Integrated Device Technology, Inc.83940D DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS CLK Input Pulldown Clock input. LVCMOS / LVTTL interface levels. Clock select input. Selects LVCMOS / LVTTL clock 4 CLK SEL Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs when LOW. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ Inverting differential LVPECL clock input. 6 nPCLK Input Pulldown V /2 default when left oating. DD 7, 21 V Power Core supply pins. DD 8, 16, 29 V Power Output supply pins. DDO 9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13, 15, 18, 19, 20, 22, Q12, Q11, Q10, Q9, Q8, Output Clock outputs. LVCMOS / LVTTL interface levels. 23, 24, 26, 27, 28, Q7, Q6, Q5, Q4, Q3, 30, 31, 32 Q2, Q1, Q0 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Power Dissipation Capacitance C 6pF PD (per output) R Input Pullup Resistor 51 K PULLup R Input Pulldown Resistor 51 K PULLDOWN R Output Impedance 18 28 OUT TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK SEL PCLK, nPCLK LVCMOS CLK 0 Selected De-selected 1 De-selected Selected TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity CLK SEL LVCMOS CLK PCLK nPCLK Q0:Q17 0 0 1 LOW Differential to Single Ended Non Inverting 0 1 0 HIGH Differential to Single Ended Non Inverting Biased 0 0 LOW Single Ended to Single Ended Non Inverting NOTE 1 Biased 0 1 HIGH Single Ended to Single Ended Non Inverting NOTE 1 0 Biased NOTE 1 0 HIGH Single Ended to Single Ended Inverting 0 Biased NOTE 1 1 LOW Single Ended to Single Ended Inverting 1 0 LOW Single Ended to Single Ended Non Inverting 1 1 HIGH Single Ended to Single Ended Non Inverting NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single Ended Levels. LOW SKEW, 1-TO-18 2 REVISION B 3/25/15 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER