GND GND Q2 Q6 VDDO VDDO Q1 Q7 GND GND Q0 Q8 VDDO VDDO GND GND Low Skew, 1-to-9 83947I-147 Data Sheet LVCMOS/LVTTL Fanout Buffer GENERAL DESCRIPTION FEATURES The 83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL Nine LVCMOS/LVTTL outputs Fanout Buffer. The low impedance LVCMOS/LVTTL outputs Selectable CLK0 and CLK1 can accept the following are designed to drive 50 series or parallel terminated input levels: LVCMOS and LVTTL transmission lines. The effective fanout can be increased from 9 to 18 by utilizing the ability of the outputs to drive two series Maximum output frequency: 250MHz terminated lines. Output skew: 115ps (maximum) Guaranteed output and part-to-part skew characteristics make Part-to-part skew: 500ps (maximum) the 83947I-147 ideal for high performance, 3.3V or 2.5V single ended applications. Additive phase jitter, RMS: 0.02ps (typical) 3.3V Full 3.3V or 2.5V operating supply -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 GND GND 1 24 CLK SEL Q3 2 23 CLK0 VDDO 3 22 CLK1 Q4 4 21 ICS83947I-147 CLK EN GND 5 20 OE Q5 6 19 VDD VDDO 7 18 GND GND 17 8 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 2016 Integrated Device Technology, Inc 1 Revision A March 18, 201683947I-147 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 8, 9, 12, 16, 17, 20, GND Power Power supply ground. 24, 25, 29, 32 Clock select input. When HIGH, selects CLK1. When LOW, 2 CLK SEL Input Pullup selects CLK0. LVCMOS / LVTTL interface levels. 3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 5 CLK EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. 7V Power Core supply pin. DD 10, 14, 18, 22, 27, 31 V Power Output supply pins. DDO 11, 13, 15, 19, 21, 23, Q8, Q7, Q6, Q5, Q4, Q0 thru Q8 clock outputs. Output 26, 28, 30 Q3, Q2, Q1, Q0 LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Power Dissipation Capacitance C 12 pF PD (per output) R Input Pullup Resistor 51 K PULLUP R Output Impedance 7 OUT TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE Control Inputs Output OE CLK EN Q0:Q8 0 X Hi-Z 1 0 LOW 1 1 Follows CLK input 2016 Integrated Device Technology, Inc 2 Revision A March 18, 2016