GND GND Q2 Q6 VDDO VDDO Q1 Q7 GND GND Q0 Q8 VDDO VDDO GND GND Low Skew, 1-to-9 83947 Data Sheet LVCMOS Fanout Buffer GENERAL DESCRIPTION FEATURES The 83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low 9 LVCMOS/LVTTL outputs impedance LVCMOS/LVTTL outputs are designed to drive 50 series Selectable CLK0 and CLK1 can accept the following or parallel terminated transmission lines. The effective fanout can be input levels: LVCMOS and LVTTL increased from 9 to 18 byutilizing the ability of the outputs to drive two series terminated lines. Maximum output frequency: 110MHz Guaranteed output and part-to-part skew characteristics make the Output skew: 500ps (maximum) 83947I ideal for high performance, single ended applications that also Part-to-part skew: 2ns (maximum) require a limited output voltage. 3.3V operating supply -40C to 85C ambient operating temperature Lead-Free package available BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 GND 1 24 GND CLK SEL 2 23 Q3 CLK0 3 22 VDDO CLK1 4 21 Q4 ICS83947I CLK EN 5 20 GND OE 6 19 Q5 VDD 7 18 VDDO GND 17 GND 8 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 2016 Integrated Device Technology, Inc 1 Revision B March 17, 201683947 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 8, 9, 12, 16, 17, 20, GND Power Power supply ground. 24, 25, 29, 32 Clock select input. When HIGH, selects CLK1. When LOW, 2 CLK SEL Input Pullup selects CLK0. LVCMOS / LVTTL interface levels. 3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 5 CLK EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. 7V Power Coree supply pin. DD 10, 14, 18, 22, 27, 31 V Power Output supply pins. DDO 11, 13, 15, 19, 21, 23, Q8, Q7, Q6, Q5, Q4, Q0 thru Q8 clock outputs. Output 26, 28, 30 Q3, Q2, Q1, Q0 LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Power Dissipation Capacitance C 25 pF PD (per output) R Input Pullup Resistor 51 K PULLUP R Input Pulldown Resistor 51 K PULLDOWN R Output Impedance 5 7 12 OUT TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE Control Inputs Output OE CLK EN Q0:Q8 0 X Hi-Z 1 0 LOW 1 1 Follows CLK input 2016 Integrated Device Technology, Inc 2 Revision B March 17, 2016