Low Skew, 1-to-1 Differential- 83948I-147 to-LVCMOS/ LVTTL Fanout Buffer Data Sheet General Description Features The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVT- Twelve LVCMOS/LVTTL outputs TL Fanout Buffer. The 83948I-147 has two selectable clock inputs. Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input The CLK, nCLK pair can accept most standard differential input lev- CLK/nCLK pair can accept the following differential els. The LVCMOS CLK can accept LVCMOS or LVTTL input levels. input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fa- LVCMOS CLK supports the following input types: LVCMOS, LVTTL nout can be increased from 12 to 24 by utilizing the ability of the out- puts to drive two series terminated lines. Output frequency: 350MHz The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V Additive phase jitter, RMS: 0.14ps (typical) core/2.5V output operating supply modes. Guaranteed output and Output skew: 100ps (maximum), 3.3V5% part-to-part skew characteristics make the 83948I-147 ideal for those clock distribution applications demanding well defined performance Part-to-part skew: 1ns (maximum), 3.3V5% and repeatability. Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment CLK EN D Q 32 31 30 29 28 27 26 25 CLK SEL 1 GND LVCMOS CLK 24 1 Q0 LVCMOS CLK 2 23 Q4 CLK 0 nCLK CLK 3 22 VDDO Q1 Q5 nCLK 4 21 CLK SEL Q2 CLK EN GND 5 20 Q3 OE 6 19 Q6 VDD 7 VDDO 18 Q4 GND 8 Q7 17 Q5 9 10 11 12 13 14 15 16 Q6 Q7 83948I-147 Q8 32-Lead LQFP Q9 7mm x 7mm x 1.4mm package body Y Package Q10 Top View Q11 OE 2016 Integrated Device Technology, Inc 1 Revision D March 30, 2016 Q11 GND VDDO Q0 Q10 VDDO Q1 GND Q9 GND VDDO Q2 Q8 VDDO GND Q383948I-147 Data Sheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description Clock select input. When HIGH, selects LVCMOS CLK input. 1 CLK SEL Input Pullup When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels. LVCMOS CL 2 Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. K 3 CLK Input Pullup Non-inverting differential clock input. 4 nCLK Input Pulldown Inverting differential clock input. 5 CLK EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. Output enable pin. When LOW, outputs are in an High-impedance state. 6 OE Input Pullup when HIGH, outputs are active. LVCMOS/LVTTL interface levels. 7V Power Power supply pin. DD 8, 12, 16, GND Power Power supply ground. 20, 24, 28, 32 Q11, Q10, 9, 11, 13, Q9, Q8, Q7, 15, 17, 19, Q6, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 21, 23, 25, Q5, Q4, Q3, 27, 29, 31 Q2, Q1, Q0 10, 14, 18, V Power Output supply pins. DDO 22, 26, 30 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP Input Pulldown Resistor 51 k R PULLDOWN Power Dissipation Capacitance C 12 pF PD (per output) Output Impedance 5 7 12 R OUT Function Tables Table 3A. Clock Select Function Table Control Clock Input 0 CLK/nCLK inputs selected 1 LVCMOS CLK input selected 2016 Integrated Device Technology, Inc 2 Revision D March 30, 2016