83948I Low Skew, 1-to-12 Differential-to- Datasheet LVCMOS/LVTTL Fanout Buffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The 83948I is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Twelve LVCMOS/LVTTL outputs Fanout Buffer and a member of the family of High Performance Selectable differential CLK/nCLK or LVCMOS/LVTTL clock Clock Solutions from IDT. The 83948I has two selectable clock input inputs. The CLK, nCLK pair can accept most standard differential CLK/nCLK pair can accept the following differential input levels. The LVCMOS CLK can accept LVCMOS or LVTTL input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels. The low impedance LVCMOS/LVTTL outputs are LVCMOS CLK supports the following input types: LVCMOS, designed to drive 50 series or parallel terminated transmission LVTTL lines. The effective fanout can be increased from 12 to 24 by Maximum output frequency: 250MHz utilizing the ability of the outputs to drive two series terminated Output skew: 350ps (maximum) lines. Part-to-part skew: 1.5ns (maximum) The 83948I is characterized at full 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the 3.3V core, 3.3V output 83948I ideal for those clock distribution applications demanding -40C to 85C ambient operating temperature well defined performance and repeatability. Available in lead-free (RoHS 6) package For drop in replacement part use 83948i-147 Pin Assignment Pullup CLK EN D Q 32 31 30 29 28 27 26 25 Pullup LVCMOS CLK 1 1 CLK SEL 24 GND Q0 Pullup CLK LVCMOS CLK 2 23 Q4 0 Pulldown nCLK Q1 CLK 3 22 VDDO Pullup Q5 CLK SEL nCLK 4 21 Q2 CLK EN 5 GND 20 Q3 OE 6 Q6 Block Diagram 19 Q4 VDD 7 VDDO 18 GND 8 Q7 Q5 17 9 10 11 12 13 14 15 16 Q6 Q7 83948I Q8 32-Lead LQFP Q9 7mm x 7mm x 1.4mm package body Y Package Q10 Top View Q11 Pullup OE 2016 Integrated Device Technology, Inc 1 May 19, 2016 Q11 GND VDDO Q0 Q10 VDDO GND Q1 GND Q9 VDDO Q2 Q8 VDDO GND Q383948I Datasheet Table 1. Pin Descriptions Number Name Type Description Clock select input. When HIGH, selects LVCMOS CLK input. 1 CLK SEL Input Pullup When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels. 2 LVCMOS CLK Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK Input Pullup Non-inverting differential clock input. 4 nCLK Input Pulldown Inverting differential clock input. 5 CLK EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. 6 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. 7V Power Positive supply pin. DD 8, 12, 16, GND Power Power supply ground. 20, 24, 28, 32 9, 11, 13, Q11, Q10, Q9, 15, 17, 19, Q8, Q7, Q6, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 21, 23, 25, Q5, Q4, Q3, 27, 29, 31 Q2, Q1, Q0 10, 14, 18, V Power Output supply pins. DDO 22, 26, 30 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Power Dissipation Capacitance C 25 pF PD (per output) R Output Impedance 7 OUT Function Tables Table 3A. Clock Select Function Table Control Input Clock CLK SEL CLK/nCLK LVCMOS CLK 0 Selected De-selected 1 De-selected Selected 2016 Integrated Device Technology, Inc 2 May 19, 2016