FSEL3 OE C FSEL2 GND QB FSEL1 QB2 FSEL0 QB1 GNDA QB0 V DDA V DDO B GND VDDO A V DD QA MR OE A PLL SEL OE B REF SEL GND QA GND XTAL REFOUT SEL System & DDR Clocks for Freescale 840NT4 B4/T4 Processor Systems DATA SHEET General Description Features The 840NT4 is a PLL-based clock generator designed to interface Ten LVCMOS clock outputs: four system clocks, four DDR clocks, with Freescale B4/T4 Processor systems. The clock generator offers one RTC output, and one 25MHz reference clock low jitter, low-skew clock outputs, frequency margining (0.025 - Selectable input reference: crystal oscillator interface or 0.312MHz step granularity), and spread spectrum clocking that differential LVPECL input meets the ever-growing demands of Freescales next generation Output Frequency Range: 25MHz - 200MHz processors. 2 Serial Interface: I C programmable Frequency Margining in <0.312MHz steps Spread spectrum for EMI reduction VCO range: 2GHz 2.4GHz Voltage supply modes: Core (V , V , V ) all core voltages must be identical DD DDXTAL DDA Output (V ,V , V V , V ) DDO A DDO B DDO C, DDO REF0 DDO REF1 Core / Output 3.3V / 3.3V 3.3V / 2.5V 3.3V / 1.8V 2.5V / 2.5V 2.5V / 1.8V Output voltage levels are independently selectable -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Output Frequency Reference Table Pin Assignment SYSCLK DDRCLK XTAL (MHz) FSEL 3:0 QA & QB (MHz) QC (MHz) 25 0000 66.67 66.67 3635 3433 32 31 3029 28 27 26 25 25 0001 66.67 100 37 24 25 0010 66.67 125 38 23 25 0011 66.67 133.33 39 22 40 25 0100 100 66.67 21 20 41 25 0101 100 100 840NT4 42 19 25 0110 100 125 43 18 25 0111 100 133.33 44 17 25 1000 125 66.67 45 16 46 25 1001 125 100 15 47 14 25 1010 125 125 48 13 25 1011 125 133.33 1 2 3 4 5 6 7 8 9 10 11 12 25 1100 133.33 66.67 25 1101 133.33 100 25 1110 133.33 125 25 1111 133.33 133.33 840NT4 48-lead, 7.0mm x 7.0mm VFQFN REVISION 1 6/16/14 1 2014 INTEGRATED DEVICE TECHNOLOGY, INC. XTAL IN SADR XTAL OUT SSC EN VDDXTAL SDATA PCLK SCLK nPCLK VDD V GND QC DD V GND REF DDO C OE REF QC3 QREF0 QC2 VDDO REF0 QC1 VDDO REF1 QC0 V QREF1 DDO C840NT4 DATA SHEET Block Diagram VDD Pullup OE REF Pullup OE A Pullup OE B VDDO REF0 Pulldown REFOUT SEL 0= 8 QREF0 (RTC) 1= 16 VDDO REF1 Pullup PLL SEL Pulldown QREF1 REF SEL XTAL1 IN VDDO A OSC XTAL1 OUT Pulldown QA PCLK VDDA nPCLK Pullup/ Pulldown VDDO B Phase Detector QB0 (System Clocks) VCO N1 MM QB1 Pulldown MR QB2 Pulldown FSEL 3:0 Configuration Interface Logic Pulldown (Frequency) SSC EN VDDO C 2 SCLK IC Control SDATA (Frequency, Pulldown Spread-Spectrum Clocking) SADR QC0 N2 Pullup OE C QC1 (DDR Clocks) QC2 QC3 REVISION 1 6/16/14 2 SYSTEM & DDR CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS