Crystal-to-LVCMOS/LVTTL 840S05I Frequency Synthesizer Data Sheet General Description Features The 840S05I is a five output LVCMOS/LVTTL Frequency Four single-ended LVCMOS/LVTTL clock outputs Synthesizer accepting crystal or single-ended reference clock One REF OUT LVCMOS/LVTTL clock output inputs. The 840S05I uses a 25MHz parallel resonant crystal to Selectable crystal oscillator interface, 25MHz, 18pF parallel generate 33.33MHz 166.67MHz clock signals, replacing solutions resonant crystal or LVCMOS/LVTTL single-ended reference input requiring multiple oscillator and fan-out buffer solution. The device Supports the following output frequencies on either bank: supports output slew rate control with two slew select pins 33.33MHz, 50MHz, 66.67MHz, 83.33MHz, 100MHz, 125MHz, (SLEW 1:0 ). The VCO operates at a frequency of 2GHz. The device 133.33MHz, and 166.67MHz has 2 output banks, Bank A with two 33.33MHz 166.67MHz VCO: 2GHz LVCMOS/LVTTL outputs and Bank B with two 33.33MHz Slew rate control 166.67MHz LVCMOS/LVTTL outputs. Output supply modes: The two banks have their own dedicated frequency select pins and Core/Output can be independently set for frequencies in the ranges mentioned 3.3V/3.3V above. Designed for networking and industrial applications, the 3.3V/2.5V 840S05I can also drive the high-speed clock inputs of -40C to 85C ambient operating temperature communication processors, DSPs, switches and bridges. Lead-free (RoHS 6) packaging Block Diagram Pin Assignment 2 Pullup F SELA 0, 2 Pulldown QA0 F SELA1 24 23 22 21 20 19 18 17 25MHz NA VDD 25 16 F SELB0 XTAL IN QA1 OSC 0 nc 26 15 MR/nOE XTAL OUT PLL GND 27 14 F SELB1 VCO 2GHz F SELA0 28 13 GND QB0 Pulldown REF IN 1 F SELA1 29 12 nc NB SLEW0 30 11 REF OUT Pulldown REF SEL QB1 M = 80 SLEW1 31 10 VDDO REF F SELA2 32 2 9 nREF OE Pulldown SLEW 1:0 12345678 Pulldown MR/nOE REF OUT 3 Pulldown F SELB 2:0 Pullup nREF OE 840S05I 32-Lead TQFP, E-Pad 7mm x 7mm x 1mm package body Y Package Top View 2016 Integrated Device Technology, Inc 1 Revision A April 11, 2016 VDDA GND VDD QA0 XTAL OUT QA1 XTAL IN VDDO A GND GND REF SEL QB0 REF IN QB1 F SELB2 VDDO B840S05I Data Sheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1V Power Analog supply pin. DDA 2, 25 V Power Core supply pin. DD 3, XTAL OUT, Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 4 XTAL IN 5, 13, GND Power Power supply ground. 20, 24, 27 6 REF SEL Input Pulldown Reference select pin. See Table 3C. LVCMOS/LVTTL interface levels. 7 REF IN Input Pulldown Single-ended 25MHz reference clock input. LVCMOS/LVTTL interface levels. 8, F SELB2, Frequency select pins for Bank B outputs. See Table 3A. 14, F SELB1, Input Pulldown LVCMOS/LVTTL interface levels. 16 F SELB0 Active low REF OUT enable/disable pin. See Table 3D. 9 nREF OE Input Pullup LVCMOS/LVTTL interface levels. 10 V Power Output supply pin for REF OUT clock output. DDO REF 11 REF OUT Output Single-ended LVCMOS/LVTTL reference clock output. 12, 26 nc Unused No connect. Active HIGH Master Reset. Active LOW output enable. See Table 3E. 15 MR/nOE Input Pulldown LVCMOS/LVTTL interface levels. 17 V Power Output supply pin for QBx outputs. DDO B 18, 19 QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 21 V Power Output supply pin for QAx outputs. DDO A 22, 23 QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 28, F SELA0, Frequency select pins for Bank A outputs. See Table 3A. Input Pullup 32 F SELA2 LVCMOS/LVTTL interface levels. Frequency select pin for Bank A outputs. See Table 3A. 29 F SELA1 Input Pulldown LVCMOS/LVTTL interface levels. 30, SLEW0, Slew rate select pins for LVCMOS/LVTTL clock output. See Table 3B. Input Pulldown 31 SLEW1 LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2016 Integrated Device Technology, Inc 2 Revision A April 11, 2016