Clock Generator for Cavium 8413S09 Processors DATA SHEET General Description Features The 8413S09 is a PLL-based clock generator specifically designed Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz for the Cavium Networks OCTEON Plus 58xx family of processors clocks for PCI Express, sRIO, XAUI, SGMII and HCSL interface and Advanced Mezzanine Card (AMC) applications. This high levels performance device is optimized to generate the processor core Two fix frequency 100MHz clocks (QDx, nQDx) for PCI Express reference clock, the PCI-Express, sRIO, XAUI, and SGMII SerDes and HCSL interface levels reference clocks and the clock for Gigabit Ethernet MACs or PHYs. One LVCMOS/LVTTL QREF output, 15 output impedance The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for processor Selectable external crystal or differential (single-ended) input core reference, PCI-Express, sRIO, XAUI, and SGMII SerDes source interfaces. The output frequencies are generated from a 25MHz Crystal oscillator interface designed for 25MHz, parallel resonant external input source or an external 25MHz parallel resonant crystal crystal.The industrial temperature range of the 8413S09 supports a variety of communications, networking, processor, DSP, data Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, acquisition, storage and I/O application requirements. LVHSTL, HCSL input levels Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels Supply Modes: Applications Full 3.3V (HSCL and QREF0) Mix 3.3V core /2.5V (QREF0) Systems using Cavium Networks OCTEON Plus 58XX processors -40C to 85C ambient operating temperature Advanced Mezzanine Cards Lead-free (RoHS 6) packaging Integrated Control and Data Plane Solutions Enterprise, Data Center, Edge and Core Networks Pin Assignment Storage Network Appliances WAN Optimization Appliances Wired and Wireless Network Security Web Servers and Exchange Servers 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 OE C 35 FSEL A0 2 nQC1 3 34 QC1 FSEL A1 FSEL B0 4 33 nQC0 32 FSEL B1 5 QC0 FSEL C0 6 31 V DDO C 6 FSEL C1 7 30 V DDO B V 29 nQB1 8 DDA XTAL IN 9 28 QB1 10 27 nQB0 XTAL OUT 11 26 QB0 REF SEL GND 12 25 OE B 13 14 15 16 17 18 19 20 21 22 23 24 SLQ PP PP 9)4)1 3DFNDJH REVISION B 1/27/15 1 2015 INTEGRATED DEVICE TECHNOLOGY, INC. V V DD DDO QREF PLL SEL QREF0 OE REF CLK nCLK nMR OE A OE D V nQD1 DDO A QD1 QA0 nQA0 nQD0 QD0 QA1 nQA1 V DDO D GND V DD V IREF DD8413S09 DATA SHEET Block Diagram Pulldown 2 FSELA 0:1 Clock Pulldown 2 Output 00=100MHz 2 FSELB 0:1 QA0, QA1 Control 01=125MHz Pulldown 2 2 FSELC 0:1 Logic 10=156.25MHz nQA0, nQA1 11=312.5MHz Pullup OE A Pullup PLL SEL 00=100MHz 2 Pullup QB0, QB1 01=125MHz REF SEL 2 10=156.25MHz nQB0, nQB1 11=312.5MHz Pulldown Pullup CLK OE B PU/PD 0 nCLK 0 00=100MHz 2 XTAL IN QC0, QC1 01=125MHz OSC 1 2 10=156.25MHz nQC0, nQC1 11=312.5MHz XTAL OUT Pullup 1 PLL OE C IREF 2 QD0, QD1 100MHz 2 nQD0, nQD1 Pullup OE D QREF0 Pullup Pullup nMR OE REF CLOCK GENERATOR FOR CAVIUM PROCESSORS 2 REVISION B 1/27/15