FemtoClock Crystal-to-0.7V Differential ICS841484I
HCSL Clock Generator
DATA SHEET
General Description Features
The ICS841484I is an optimized PCIe and sRIO clock generator. Four 0.7V differential HCSL outputs: configurable for PCIe
(100MHz or 200MHz) and sRIO (125MHz) clock signals
The device uses a 25MHz parallel resonant crystal to generate
100MHz, 125MHz, 200MHz and 400MHz clock signals, replacing
One LVCMOS/LVTTL reference clock output
solutions requiring multiple oscillator and fanout buffer solutions. The
Selectable crystal oscillator interface, 25MHz, 18pF parallel
device has excellent phase jitter suitable to clock components
resonant crystal or LVCMOS/LVTTL single-ended reference clock
requiring precise and low jitter PCIe, sRIO or both clock signals. The input
device also supports a configurable spread-spectrum generation for
Supports the following output frequencies: 100MHz, 125MHz,
PCIe applications. Designed for telecom, networking and industrial
200MHz or 400MHz
applications, the ICS841484I can also drive the high-speed sRIO
VCO frequency range: 950MHz - 1.25GHz
and PCIe SerDes clock inputs of communications processors,
Configurable spread-spectrum generation for PCIe
DSPs, switches and bridges.
PLL bypass and output enable
RMS phase jitter @ 200MHz, using a 25MHz crystal
(12kHz 20MHz): 1.21ps (typical)
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant (REF_OUT disabled)
Full 3.3V operating supply
-40C to 85C ambient operating temperature
Available in lead-free (RoHS 6) packages
Block Diagram
Pulldown
OE_REFOUT
25MHz
REF_OUT
25MHz
=
XTAL_IN N
Q0
1
0
OSC
nQ0
FemtoClock
XTAL_OUT
PLL
0
Spread-Spectrum Q1
Pulldown
REF_IN
1
Pin Assignment
nQ1
Pulldown
REF_SEL
M =
Q2
40, 48
nQ2
IREF
32 31 30 29 28 27 26 25
Pulldown
SSM
Q3 XTAL_IN 1 24 V
DD
Pulldown
BYPASS XTAL_OUT 2 23 FSEL1
nQ3
ICS841484I
MR/nOE 3 22 FSEL0
2
Pullup:Pulldown
FSEL[1:0]
32-Lead VFQFN
V REF_OUT
DD 4 21
5mm x 5mm x 0.925mm
Pulldown
MR/nOE
5 20
Q0 OE_REFOUT
package body
nQ0 6 19 GND
K Package
Q1 7 18 nc
Top View
nQ1 8 17 nc
9 10 11 12 13 14 15 16
ICS841484DKI REVISION A NOVEMBER 7, 2012 1 2012 Integrated Device Technology, Inc.
GND GND
Q2 REF_IN
nQ2 REF_SEL
Q3 VDD
VDDA
nQ3
VDD BYPASS
nc IREF
nc SSM
ICS841484I Data Sheet FEMTOCLOCK CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Table 1. Pin Descriptions
Number Name Type Description
1, XTAL_IN, Parallel resonant crystal interface. XTAL_OUT is the output,
Input
2 XTAL_OUT XTAL_IN is the input. (PLL reference.)
3 MR/nOE Input Pulldown Master reset. LVCMOS/LVTTL interface levels. See Table 3D.
4, 14, 24, 29 V Power Core supply pins.
DD
5, 6 Q0, nQ0 Output Differential output pair. HCSL interface levels.
7, 8 Q1, nQ1 Output Differential output pair. HCSL interface levels.
9, 19, 32 GND Power Power supply ground.
10, 11 Q2, nQ2 Output Differential output pair. HCSL interface levels.
12, 13 Q3, nQ3 Output Differential output pair. HCSL interface levels.
15, 16, 17, 18 nc Unused No connect.
20 OE_REFOUT Input Pulldown Output enable pin. LVCMOS/LVTTL interface levels. See Table 3F.
Reference clock output. LVCMOS/LVTTL interface levels. In PCIe Gen 2 and
21 REF_OUT Output
Gen 3 applications, the REF_OUT output should be disabled.
22 F_SEL0 Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B.
23 F_SEL1 Input Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B.
25 SSM Input Pulldown Spread-spectrum selection. LVCMOS/LVTTL interface levels. See Table 3A.
) from this pin to ground provides a
An external fixed precision resistor (475
26 IREF Output
reference current used for differential current-mode Qx, nQx clock outputs.
Selects PLL operation/PLL bypass operation. See Table 3C.
27 BYPASS Input Pulldown
LVCMOS/LVTTL interface levels.
28 V Power Analog supply pin.
DDA
Reference select. Selects the input reference source.
30 REF_SEL Input Pulldown
LVCMOS/LVTTL interface levels. See Table 3E.
31 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C Input Capacitance 4pF
IN
R Input Pulldown Resistor 51 k
PULLDOWN
R Input Pullup Resistor 51 k
PULLUP
R Output Impedance REF_OUT 27
OUT
ICS841484DKI REVISION A NOVEMBER 7, 2012 2 2012 Integrated Device Technology, Inc.