FemtoClock NG Crystal-to-HCSL 841602 Clock Generator DATASHEET GENERAL DESCRIPTION FEATURES The 841602 is an optimized PCIe and Two differential clock outputs: con gurable for PCIe (100MHz) and sRIO (125MHz) clock signals sRIO clock generator. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, Selectable crystal oscillator interface, 25MHz, 18pF parallel replacing solutions requiring multiple oscilla- resonant crystal or LVCMOS/LVTTL single-ended reference tor and fanout buffer solutions. The device has excellent clock input phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Supports the following output frequencies: Designed for telecom, networking and industrial appli- 100MHz or 125MHz cations, the 841602 can also drive the high-speed sRIO and PCIe VCO: 500MHz SerDes clock inputs of communication processors, DSPs, switches PLL bypass and output enable and bridges. PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant RMS phase jitter, 125MHz, using a 25MHz crystal: (1.875MHz 20MHz): 0.45ps (typical) Full 3.3V power supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT XTAL IN Q0 REF SEL VDDA 1 28 1 0 OSC REF IN 27 BYPASS 2 nQ0 VDD IREF 26 FemtoClock 3 XTAL OUT N GND FSEL 0 4 25 PLL 4 Pulldown VCO = 500MHz Q1 REF IN 24 VDD 1 XTAL IN 5 5 (default) nQ1 XTAL OUT 23 6 nQ1 Q1 MR/nOE 22 7 Pulldown REF SEL nQ0 VDD 8 21 nc 20 Q0 9 M = 20 nc 19 GND 10 IREF nc nc 11 18 nc nc 12 17 Pulldown BYPASS nc GND 13 16 nc Pulldown VDD 15 14 FSEL Pulldown 841602 MR/nOE 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View 841602 REVISION A 4/15/15 1 2015 Integrated Device Technology, Inc.841602 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Reference select. Selects the input reference source. 1 REF SEL Input Pulldown LVCMOS/LVTTL interface levels. See Table 3D. 2 REF IN Input Pulldown LVCMOS/LVTTL PLL reference clock input. 3, 8, 14, 24 V Power Core supply pins. DD 4, 13, 19 GND Power Power supply ground. 5, XTAL IN, Parallel resonant crystal interface. XTAL OUT is the output, Input 6 XTAL OUT XTAL IN is the input. Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance (HiZ). When 7 MR/nOE Input Pulldown logic LOW, the internal dividers and the outputs are enabled. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C. 9, 10, 11, 12, 15, 16, nc Unused No connect. 17, 18 20, 21 Q0, nQ0 Output Differential output pair. PCI Express interface levels. 22, 23 Q1, nQ1 Output Differential output pair. PCI Express interface levels. 25 FSEL Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A. HCSL current reference resistor output. An external xed precision resistor 26 IREF Output (475) from this pin to ground provides a reference current used for differen- tial current-mode Qx/nQx clock outputs. Selects PLL operation/PLL bypass operation. Asynchronous function. LLVC- 27 BYPASS Input Pulldown MOS/LVTTL interface levels. See Table 3B. 28 V Power Analog supply pin. DDA NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN TABLE 3A. FSEL FUNCTION TABLE (f = 25MHZ) TABLE 3B. BYPASS FUNCTION TABLE ref Input Outputs Input FSEL N Q0:7/nQ0:7 BYPASS PLL Con guration 0 5 VCO/5 (100MHz) PCIe (default) 0 PLL enabled (default) 1 4 VCO/4 (125MHz) sRIO 1 PLL bypassed (f = f N) OUT REF TABLE 3C. MR/nOE FUNCTION TABLE TABLE 3D. REF SEL FUNCTION TABLE Input Input MR/nOE Function REF SEL Input Reference 0 Outputs enabled (default) 0 XTAL (default) 1 Device reset, outputs disabled (high-impedance) 1 REF IN FEMTOCLOCKS CRYSTAL-TO-HCSL 2 REVISION A 4/15/15 CLOCK GENERATOR