VDDA FREQ SEL VDD nc nc XTAL IN XTAL OUT GND FemtoClock Crystal-to-LVDS 844008I-46 Clock Generator DATA SHEET GENERAL DESCRIPTION FEATURES The 844008I-46 is a 10Gb Ethernet Clock Generator and a member Eight differential LVDS outputs of the HiPerClocks family of high performance devices from Crystal oscillator interface designed for 18pF parallel resonant IDT. The 844008I-46 can synthesize 156.25MHz or 100MHz with crystals a 25MHz crystal. It has a total of 8 LVDS outputs. The 844008I-46 Supports the following output frequencies: has excellent phase jitter performance and is packaged in a 32 156.25MHz or 100MHz Lead VFQFN package, making it ideal for use in systems with VCO frequency: 625MHz or 600MHz limited board space. RMS phase jitter 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical) Full 2.5V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages For functional replacement part use 8T49N285 FREQUENCY SELECT FUNCTION TABLE Input XTAL Frequency (MHz) FREQ SEL FB Divider Output Divider VCO (MHz) Output Frequency (MHz) 25 0 25 4 625 156.25 (default) 25 1 24 6 600 100 BLOCK DIAGRAM PIN ASSIGNMENT Pullup OE 25MHz 8 Q0:Q7 XTAL IN OSC Phase VCO 4 or 625MHz or Detector 8 nQ0:nQ7 6 600MHz 32 31 30 29 28 27 26 25 XTAL OUT Q0 nc 1 24 OE nQ0 2 23 FB = 25 or 24 GND GND ICS844008I-46 3 22 32-Lead VFQFN nQ7 Q1 4 21 5mm x 5mm x 0.925mm pack- Q7 nQ1 5 20 Pulldown FREQ SEL age body VDDO VDDO 6 19 K Package nQ6 Q2 7 Top View 18 nQ2 Q6 8 17 9 10 11 12 13 14 15 16 844008I-46 REVISION A 11/6/15 1 2015 Integrated Device Technology, Inc. Q3 nQ3 GND Q4 nQ4 VDDO Q5 nQ5844008I-46 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels. 3, 11, 22, 32 GND Power Power supply ground. 4, 5 Q1, nQ1 Ouput Differential output pair. LVDS interface levels. 6, 14, 19 V Power Output supply pins. DDO 7, 8 Q2, nQ2 Output Differential output pair. LVDS interface levels. 9, 10 Q3, nQ3 Output Differential output pair. LVDS interface levels. 12, 13 Q4, nQ4 Output Differential output pair. LVDS interface levels. 15, 16 Q5, nQ5 Output Differential output pair. LVDS interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVDS interface levels. 20, 21 Q7, nQ7 Output Differential output pair. LVDS interface levels. Output enable pin. When LOW, outputs are disabled. When HIGH. outputs 23 OE Input Pullup are enabled. LVCMOS/LVTTL interface levels. See Table 3. 24, 28, 29 nc Unused No connect. 25 V Power Analog supply pin. DDA 26 FREQ SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 27 V Power Core supply pin. DD 30, XTAL IN, Parallel resonant crystal interface. XTAL OUT is the output, Input 31 XTAL OUT XTAL IN is the input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP TABLE 3. OE FUNCTION TABLE Inputs Outputs OE Q 0:7 /nQ 0:7 1 Enabled (default) 0 Hi-Z FEMTOCLOCK CRYSTAL-TO-LVDS 2 REVISION A 11/6/15 CLOCK GENERATOR