nCLK VDD Q15 nQ15 Q14 nQ14 GND Q13 nQ13 Q12 nQ12 VDD ICS8501 Integrated Circuit LOW SKEW, 1-TO-16 DIFFERENTIAL CURRENT MODE Systems, Inc. FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8501 is a low skew, 1-to-16 Differential 16 small swing DCM outputs ICS Current Mode Fanout Buffer and a member of Translates any differential input signal (LVPECL, LVHSTL, HiPerClockS the HiPerClockS family of High Performance LVDS, DCM) to DCM levels without external bias networks Clock Solutions from ICS. The ICS8501 is de- signed to translate any differential signal levels Translates single ended input levels to DCM levels with a to small swing differential current mode (DCM) output levels. resistor bias network on the nCLK input An external reference resistor is used to set the value of the Translates single ended input levels to inverted DCM levels current supplied to an external load load/termination resistor. with a resistor bias network on the CLK input The load resistor value is chosen to equal the value of the characteristic line impedance of 50 . The ICS8501 is char- Maximum output frequency: 500MHz acterized at an operating supply voltage of 3.3V. Output skew: 100ps (maximum) The small swing outputs, accurate crossover voltage and duty Part-to-part skew: 650ps (maximum) cycle makes the ICS8501 ideal for interfacing to todays most advanced microprocessors. V : 850mV (maximum) OH 3.3V operating supply 0C to 70C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT CLK nCLK Q15 Q0 48 47 46 45 44 43 42 41 40 39 38 37 nQ15 nQ0 VDD 1 CLK 36 Q11 2 VDD 35 Q14 Q1 nQ11 3 nQ0 34 nQ1 nQ14 Q10 4 Q0 33 Q2 Q13 nQ10 5 nQ1 32 nQ2 nQ13 6 Q1 GND 31 ICS8501 Q9 7 GND 30 Q3 Q12 nQ9 8 nQ2 29 nQ3 nQ12 9 Q2 Q8 28 nQ8 10 nQ3 27 Q4 Q11 VDD 11 Q3 nQ4 nQ11 26 nc 12 VDD 25 Q5 13 14 15 16 17 18 19 20 21 22 23 24 Q10 nQ5 nQ10 Q6 Q9 nQ6 nQ9 Q7 48-Lead LQFP Q8 nQ7 nQ8 7mm x 7mm x 1.4mm body package Y Package Top View 8501BY www.icst.com/products/hiperclocks.html REV. B OCTOBER 3, 2003 1 RREF VDD Q7 nQ7 Q6 nQ6 GND Q5 nQ5 Q4 nQ4 VDDICS8501 Integrated Circuit LOW SKEW, 1-TO-16 DIFFERENTIAL CURRENT MODE Systems, Inc. FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Neumber NeamTnyp Descriptio 1V, 11, 14, 24, 25, 35, 38, 48 P.ower Positive supply pins DD 21, 3 Qt11, nQ1O.utpu Differential output pair. Differential current mode interface levels 40, 5 Qt10, nQ1O.utpu Differential output pair. Differential current mode interface levels 6D, 19, 30, 43 GrNP.owe Power supply ground 79, 8 Qt9, nQO.utpu Differential output pair. Differential current mode interface levels 98, 10 Qt8, nQO.utpu Differential output pair. Differential current mode interface levels 1c2 ndU.nuse No connect Reference current input. Used to set the output current. 1F3 RtRE Inpu Connect to 475 resistor to ground. 175, 16 Qt7, nQO.utpu Differential output pair. Differential current mode interface levels 167, 18 Qt6, nQO.utpu Differential output pair. Differential current mode interface levels 250, 21 Qt5, nQO.utpu Differential output pair. Differential current mode interface levels 242, 23 Qt4, nQO.utpu Differential output pair. Differential current mode interface levels 236, 27 Qt3, nQO.utpu Differential output pair. Differential current mode interface levels 228, 29 Qt2, nQO.utpu Differential output pair. Differential current mode interface levels 3K6 CtLI.npu Non inverting differential clock input 3K7 ntCLI.npu Inverting differential clock input 359, 40 Qt15, nQ1O.utpu Differential output pair. Differential current mode interface levels 441, 42 Qt14, nQ1O.utpu Differential output pair. Differential current mode interface levels 434, 45 Qt13, nQ1O.utpu Differential output pair. Differential current mode interface levels 426, 47 Qt12, nQ1O.utpu Differential output pair. Differential current mode interface levels TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 2Fp IN Power Dissipation Capacitance C V=63.465V, f = 250MHz 4F. p PD DD (per output) R Output Impedance 1K4 W OUT TABLE 3. FUNCTION TABLE Isnputs Output Iynput to Output Mode Polarit CKLK n5CL Q50:Q1 nQ0:nQ1 01 0 1Dgifferential to Differential Non Invertin 10 1 0Dgifferential to Differential Non Invertin 01B0iased NOTE 1Sgingle Ended to Differential Non Invertin 11B1iased NOTE 0Sgingle Ended to Differential Non Invertin B0iased NOTE 1 1 0Sgingle Ended to Differential Invertin B1iased NOTE 1 0 1Sgingle Ended to Differential Invertin NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single Ended Levels. 8501BY www.icst.com/products/hiperclocks.html REV. B OCTOBER 3, 2003 2