CLK0 12:1 Single-ended Multiplexer 850S1201 Datasheet General Description Features The 850S1201 is a low skew12:1 Single-ended Clock Multiplexer. 12:1 single-ended multiplexer The 850S1201 has 12 selectable single-ended clock inputs and 1 Nominal output impedance: 20 (V = 3.3V) DD single- ended clock output. The device operates up to 250MHz and Maximum output frequency: 250MHz is packaged in a 20 TSSOP package. Propagation delay: 2.7ns (maximum) Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown CLK SEL0 CLK8 1 20 CLK7 CLK9 2 19 CLK6 Pulldown CLK SEL1 CLK10 3 18 CLK5 CLK11 4 17 CLK4 Pulldown CLK SEL2 VDD 5 16 CLK3 Pulldown CLK SEL3 CLK SEL0 6 15 CLK2 CLK SEL1 7 14 CLK1 CLK SEL2 8 13 Pulldown CLK0 CLK SEL3 9 12 GND OE Q 10 11 Pulldown CLK1 850S1201 20-Lead TSSOP Q 6.50mm x 4.40mm x 0.925mm package body Pulldown CLK10 G Package Top View Pulldown CLK11 Pullup OE 2016 Integrated Device Technology, Inc. 1 Revison B, February 8, 2016850S1201 Datasheet Pin Description and Pin Characteristics Table 1. Pin Descriptions Number Name Type Description 1 CLK8 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 2 CLK9 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK10 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 4 CLK11 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Power Power supply pin. 5V DD 6, CLK SEL0, 7. CLK SEL1, Input Pulldown Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels. 8, CLK SEL2, 9 CLK SEL3 10 OE Input Pullup Output enable pin for Q output. LVCMOS/LVTTL interface levels. 11 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 12 GND Power Power supply ground. 13 CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 14 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 15 CLK2 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 16 CLK3 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 17 CLK4 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 18 CLK5 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 19 CLK6 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 20 CLK7 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN V = 3.465V 10 pF DD C Power Dissipation Capacitance PD V = 2.625V 8 pF DD R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.3V5% 20 DD R Output Impedance OUT V = 2.5V5% 25 DD 2016 Integrated Device Technology, Inc. 2 Revison B, February 8, 2016