Q9 nQ14 nQ9 Q14 Q8 nQ15 nQ8 Q15 GND GND OE2 CLK OE1 nCLK GND GND nQ7 Q0 Q7 nQ0 nQ6 Q1 Q6 nQ1 ICS8516I Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip DATA SHEET GENERAL DESCRIPTION FEATURES The ICS8516I is a low skew, high performance 1- Sixteen Differential LVDS outputs ICS to-16 Differential-to-LVDS Clock Distribution Chip CLK, nCLK pair can accept the following differential HiPerClockS and a member of the HiPerClockS family of High input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Performance Clock Solutions from IDT. The ICS8516I CLK, nCLK pair can accept any differ- Maximum output frequency: 700MHz ential input levels and translates them to 3.3V LVDS output Translates any differential input signal (LVPECL, LVHSTL, levels. Utilizing Low Voltage Differential Signaling (LVDS), the SSTL, DCM) to LVDS levels without external bias networks ICS8516I provides a low power, low noise, point-to-point solu- tion for distributing clock signals over controlled impedances Translates any single-ended input signal to LVDS of 100. with resistor bias on nCLK input Dual output enable inputs allow the ICS8516I to be used in a Multiple output enable inputs for disabling unused 1-to-16 or 1-to-8 input/output mode. Guaranteed output and outputs in reduced fanout applications part-to-part skew specifications make the ICS8516I ideal for LVDS compatible those applications demanding well defined performance and repeatability. Output skew: 65ps (maximum) Part-to-part skew: 550ps (maximum) Propagation delay: 2.4ns (maximum) 3.3V operating supply -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT CLK nCLK 48 47 46 45 44 43 42 41 40 39 38 37 VDD 1 36 VDD Q0 Q15 nQ5 2 35 nQ10 nQ0 nQ15 Q5 3 34 Q10 Q1 Q14 nQ4 4 33 nQ11 nQ1 nQ14 Q4 5 32 Q11 Q2 Q13 VDD 6 31 VDD ICS8516I nQ2 nQ13 GND 7 30 GND nQ3 8 29 nQ12 Q3 Q12 nQ3 nQ12 Q3 9 28 Q12 nQ2 10 27 nQ13 Q4 Q11 Q2 11 26 Q13 nQ4 nQ11 VDD 12 25 VDD Q10 13 14 15 16 17 18 19 20 21 22 23 24 Q5 nQ5 nQ10 Q6 Q9 nQ9 nQ6 Q7 Q8 48-Lead LQFP nQ8 nQ7 7mm x 7mm x 1.4mm body package Y Package OE1 Top View OE2 ICS8516I REVISION B SEPTEMBER 10, 2009 1 2009 Integrated Device Technology, Inc.ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 1, 6, 12, VP.ower Positive supply pins DD 25, 31, 36 25, 3ntQ5, QO.utpu Differential output pair. LVDS interface levels 44, 5ntQ4, QO.utpu Differential output pair. LVDS interface levels 7, 17, 20, GrNDP.owe Power supply ground 30, 41, 44 83, 9ntQ3, QO.utpu Differential output pair. LVDS interface levels 120, 11ntQ2, QO.utpu Differential output pair. LVDS interface levels 113, 14ntQ1, QO.utpu Differential output pair. LVDS interface levels 105, 16ntQ0, QO.utpu Differential output pair. LVDS interface levels 1K8 ntCL IpnpuP.ullu Inverting differential clock input 1K9 CtL InnpuP.ulldow Non-inverting differential clock input 251, 22Qt15, nQ1O.utpu Differential output pair. LVDS interface levels 243, 24Qt14, nQ1O.utpu Differential output pair. LVDS interface levels 236, 27Qt13, nQ1O.utpu Differential output pair. LVDS interface levels 228, 29Qt12, nQ1O.utpu Differential output pair. LVDS interface levels 312, 33Qt11, nQ1O.utpu Differential output pair. LVDS interface levels 304, 35Qt10, nQ1O.utpu Differential output pair. LVDS interface levels 397, 38Qt9, nQO.utpu Differential output pair. LVDS interface levels 389, 40Qt8, nQO.utpu Differential output pair. LVDS interface levels Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15 412, 43OtE2, OEIpnpu Pullu OE1 controls outputs Q0, nQ0 thru Q7, nQ7. LVCMOS/LVTTL interface levels. 475, 46ntQ7, QO.utpu Differential output pair. LVDS interface levels 467, 48ntQ6, QO.utpu Differential output pair. LVDS interface levels NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS8516I REVISION B SEPTEMBER 10, 2009 2 2009 Integrated Device Technology, Inc.