2:2 Differential-to-HCSL Multiplexer ICS851S201I with Low Input Level Alarm Datasheet Description Features The ICS851S201I is a high-performance 2-input, 2-output Two differential HCSL output pairs Differential-to-HCSL Multiplexer. The ICS851S201I operates up to Two selectable differential clock input pairs 250MHz and accepts HCSL and other low level differential inputs CLKx, nCLKx pairs can accept HCSL level inputs levels. Input level detection circuitry is available to flag input levels that drops below a specified value and on the selected input. This Low level input detection on selected input (latched) signal is latched until the status is reset via the alarm reset input. Maximum Input frequency: 250MHz The ICS851S201I is packaged in a small 3mm x 3mm 16 lead Output skew: 5ps (typical) VFQFPN package, making it ideal for use on space constrained boards. Propagation delay: 1.4ns (typical) Additive RMS phase jitter at 133.33MHz (12kHz - 20MHz): 0.151ps (typical) Full 3.3V operating supply -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Pin Assignment Block Diagram Pulldown CLK0 0 Pullup/Pulldown Q0 nCLK0 nQ0 16 15 14 13 Pulldown CLK1 1 12 CLK0 nQ0 1 Pullup/Pulldown Q1 nCLK1 nCLK0 2 11 Q0 nQ1 CLK1 3 10 nQ1 Pulldown CLK SEL nCLK1 4 9 Q1 5 6 7 8 LLA IREF Pulldown LLAR ICS851S201I 16-Lead VFQFPN Top View ICS851S201I FEBRUARY 1, 2018 1 2018 Integrated Device Technology, Inc. VDD GND LLAR CLK SEL LLA IREF GND VDDICS851S201I Datasheet 2:2 DIFFERENTIAL-TO-HCSL MULTIPLEXER Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 CLK0 Input Pulldown Non-inverting differential HCSL clock input. Pullup/ 2 nCLK0 Input Inverting differential HCSL clock input. V /2 default when left floating. DD Pulldown 3 CLK1 Input Pulldown Non-inverting differential HCSL clock input. Pullup/ 4 nCLK1 Input Inverting differential HCSL clock input. V /2 default when left floating. DD Pulldown Power Positive supply pins. 5, 13 V DD Low Level Alarm Reset. When HIGH, resets LLA latch. Must be LOW to 6 LLAR Input Pulldown allow LLA to set. LVCMOS/LVTTL interface levels. Low Level Alarm. When HIGH, low level input has been detected on 7 LLA Output selected differential input (latched). 8, 16 GND Power Power supply ground. 9, 10 Output Differential output pair. HCSL interface levels. Q1, nQ1 11, 12 Output Differential output pair. HCSL interface levels. Q0, nQ0 External fixed precision resistor (475from this pin to ground provides a 14 IREF Input reference current used for differential current-mode Qx, nQx clock outputs. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, 15 CLK SEL Input Pulldown selects CLK0, nCLK0 inputs. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 50 k PULLDOWN R Input Pullup Resistor 50 k PULLUP ICS851S201I FEBRUARY 1, 2018 2 2018 Integrated Device Technology, Inc.