nc LOW SKEW, 1-TO-5, DIFFERENTIAL-TO- ICS85214 HSTL FANOUT BUFFER PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The ICS85214 is a low skew, high performance Five differential HSTL compatible outputs ICS 1-to-5 Differential-to-HSTL Fanout Buffer and a Selectable differential CLK0, CLK0 or LVCMOS/LVTTL clock HiPerClockS member of the HiPerClockS family of High inputs Performance Clock Solutions from IDT. The CLK0, CLK0, CLK0 pair can accept the following differential input CLK0 pair can accept most standard differential levels: LVPECL, LVDS, HSTL, HCSL, SSTL input levels. The single ended CLK1 input accepts LVCMOS or CLK1 can accept the following input levels: LVCMOS or LVTTL LVTTL input levels. Guaranteed output and part-to-part skew Output frequency up to: 700MHz characteristics make the ICS85214 ideal for those clock distri- bution applications demanding well defined performance and Translates any single-ended input signal to HSTL levels with resistor bias on CLK0 input repeatability. Output skew: 30ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 1.8ns (maximum) 3.3V core, 1.8V output operating supply 0C to 85C ambient operating temperature Industrial temperature information available upon request Available in lead-free (RoHS 6) package For functional replacement part use 8523 Block Diagram Pin Assignment Pulldown CLK EN D Q0 1 20 VDDO Q Q0 2 19 CLK EN LE Q1 3 18 VDD Pullup CLK0 nc Q1 4 17 Pulldown 0 0 Q0 CLK0 Q2 5 16 CLK1 Q0 Pulldown 1 Q2 6 15 CLK0 CLK1 1 Q3 7 14 CLK0 Q1 Q3 8 13 Q1 Pulldown CLK SEL Q4 9 12 CLK SEL Q2 GND Q4 10 11 Q2 ICS85214 Q3 20-Lead TSSOP Q3 6.5mm x 4.4mm x 0.925mm Q4 package body Q4 G Package Top View IDT / ICS HSTL FANOUT BUFFER 1 ICS85214AG REV. B JUNE 3, 2016ICS85214 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, Q0 Output Differential output pair. HSTL interface levels. 3, 4 Q1, Q1 Output Differential output pair. HSTL interface levels. 5, 6 Q2, Q2 Output Differential output pair. HSTL interface levels. 7, 8 Q3, Q3 Output Differential output pair. HSTL interface levels. 9, 10 Q4, Q4 Output Differential output pair. HSTL interface levels. 11 GND Power Power supply ground. Clock select input. When HIGH, selects differential CLK1input. When LOW, 12 CLK SEL Input Pulldown selects CLK0, CLK0 inputs. LVCMOS/LVTTL interface levels. 13, 17 nc Unused No connect. 14 CLK0 Input Pullup Inverting differential clock input. 15 CLK0 Input Pulldown Non-inverting differential LVPECL clock input. 16 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 18 V Power Positive supply pin. DD Synchronizing clock enable. When LOW, clock outputs follow clock input. 19 CLK EN Input Pulldown When HIGH, Qx outputs are forced low, Qx outputs are forced high. LVTTL/LVCMOS interface levels. 20 V Power Output supply pin. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN IDT / ICS HSTL FANOUT BUFFER 2 ICS85214AG REV. B JUNE 3, 2016