Low Skew, 1-to-5 85314I-01 Differential-to-2.5V/3.3V LVPECL Fanout Buffer DATASHEET GENERAL DESCRIPTION FEATURES The 85314I-01 is a low skew, high performance 1-to- 5 differential 2.5V/3.3V LVPECL outputs 5 Differential-to-2.5V/3.3V LVPECL Fanout Buffer.The Selectable differential CLK0, nCLK0 or LVCMOS inputs 85314I-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standarddifferential input CLK0, nCLK0 pair can accept the following differential levels. The single-ended CLK1 can accept LVCMOS or input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL LVTTL input levels. The clock enable is internally CLK1 can accept the following input levels: synchronized to eliminate runt clock pulses on the outputs during LVCMOS or LVTTL asynchronous assertion/deassertion of the clockenable pin. Maximum output frequency: 700MHz Guaranteed output and part-to-part skew character- Translates any single-ended input signal to 3.3V istics make the 85314I-01 ideal for those applications LVPECL levels with resistor bias on nCLK input demanding well de ned performance and repeatability. Output skew: 30ps (maximum), TSSOP package 50ps (maximum), SOIC package Part-to-part skew: 350ps (maximum) Propagation delay: 1.8ns (maximum) RMS phase jitter 155.52MHz (12kHz - 20MHz): 0.05ps (typical) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE -40C to 85C ambient operating temperature Available in lead-free RoHS-compliant package BLOCK DIAGRAM PIN ASSIGNMENT Q0 1 20 VCC nQ0 2 19 nCLK EN Q1 3 18 VCC nQ1 4 17 nc Q2 5 16 CLK1 nQ2 6 15 CLK0 Q3 7 14 nCLK0 nQ3 8 13 nc Q4 9 12 CLK SEL nQ4 10 11 VEE 85314I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View 85314I-01 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm Package Body M Package Top View 85314I-01 REVISION G DECEMBER 19, 2014 1 2014 Integrated Device Technology, Inc.85314I-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11 V Power Negative supply pin. EE Clock select input. When HIGH, selects CLK1 input. 12 CLK SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. 13, 17 nc Unused No connect. 14 nCLK0 Input Pullup Inverting differential clock input. 15 CLK0 Input Pulldown Non-inverting differential clock input. 16 CLK1 Input Pulldown Clock input. LVTTL / LVCMOS interface levels. 18, 20 V Power Positive supply pins. CC Synchronizing clock enable. When LOW, clock outputs follow clock input. 19 nCLK EN Input Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high. LVT- TL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Low Skew, 1-to-5 2 REVISION G 12/19/14 Differential-to-2.5V/3.3V LVPECL Fanout Buffer