Low Skew, 1-to-4 8533-01 Data Sheet Differential-to-3.3V LVPECL Fanout Buffer GENERAL DESCRIPTION FEATURES The 8533-01 is a low skew, high performance 1-to-4 Four differential 3.3V LVPECL outputs Differential-to-3.3V LVPECL Fanout Buffer. The 8533- Selectable differential CLK, nCLK or LVPECL clock inputs 01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The CLK, nCLK pair can accept the following differential PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels. The clock enable is internally synchronized to PCLK, nPCLK supports the following input types: eliminate runt pulses on the outputs during asynchronous LVPECL, CML, SSTL assertion/deassertion of the clock enable pin. Guaranteed Maximum output frequency: 650MHz output and part-to-part skew characteristics make the 8533-01 ideal for those applications demanding well de ned performance Translates any single-ended input signal to 3.3V and repeatability. LVPECL levels with resistor bias on nCLK input Output skew: 30ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 1.4ns (maximum) Additive phase jitter, RMS: 0.06ps (typical) 3.3V operating supply 0C to 70C ambient operating temperature Lead-Free package Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 8533-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View 2016 Integrated Device Technology, Inc 1 Revision F January 19, 20168533-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVC- MOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. 8, 9 nc Unused No connect. 10, 13, 18 V Power Positive supply pins. CC 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision F January 19, 2016