Low Skew, 1-to-4, Crystal Oscillator/ 8533-11 Differential-to-3.3V LVPECL Fanout Buffer DATA SHEET GENERAL DESCRIPTION FEATURES The 8533-11 is a low skew, high performance 1-to-4 Crystal 4 differential 3.3V LVPECL outputs Oscillator/Differential-to-3.3V LVPECL fanout buffer. The 8533- Selectable differential CLK, nCLK or crystal inputs 11 has selectable differential clock or crystal inputs. The CLK, nCLK pair can accept most standard differential input levels. The CLK, nCLK pair can accept the following differential clock enable is internally synchronized to eliminate runt pulses input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL on the outputs during asynchronous assertion/deassertion of Maximum output frequency: 650MHz the clock enable pin. Translates any single-ended input signal to 3.3V Guaranteed output and part-to-part skew characteristics make LVPECL levels with resistor bias on nCLK input the 8533-11 ideal for those applications demanding well de ned performance and repeatability. Output skew: 30ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 2ns (maximum) 3.3V operating supply 0C to 70C ambient operating temperature Industrial temperature information available upon request Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT D CLK EN Q LE CLK 0 Q0 nCLK XTAL1 nQ0 1 XTAL2 Q1 nQ1 CLK SEL Q2 nQ2 Q3 8533-11 nQ3 20-Lead TSSOP 6.5mm x 4.4mm x 0.92 package body G Package Top View 8533-11 REVISION E 7/9/15 1 2015 Integrated Device Technology, Inc.8533-11 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follows clock input. 2 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When LOW, selects CLK, nCLK input. 3 CLK SEL Input Pulldown When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 XTAL1 Input Pulldown Crystal oscillator input. 7 XTAL2 Input Pullup Crystal oscillator input. 8, 9 nc Unused No connect. 10, 13, 18 V Power Positive supply pins. CC 11, 12 nQ3, Q3 Output Differential clock outputs. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential clock outputs. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 K PULLUP R Input Pulldown Resistor 51 K PULLDOWN LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ 2 REVISION E 7/9/15 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER