V V CCO CCO nQ6 Q14 nQ14 Q6 nQ5 Q15 Q5 nQ15 nQ4 Q16 Q4 nQ16 nQ3 Q17 Q3 nQ17 nQ2 Q18 Q2 nQ18 Q19 nQ1 Q1 nQ19 nQ0 Q20 nQ20 Q0 V V CCO CCO Low Skew, 1-to-22 Differential-to-3.3V 8534-01 LVPECL Fanout Buffer Datasheet General Description Features The 8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL Twenty-two differential LVPECL outputs Fanout Buffer. The 8534-01 has two selectable clock inputs. The Selectable differential CLK, nCLK or LVPECL clock inputs CLK, nCLK pair can accept most standard differential input levels. CLK, nCLK pair can accept the following differential input levels: The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input LVPECL, LVDS, LVHSTL, HCSL, SSTL levels. The device is internally synchronized to eliminate runt pulses PCLK, nPCLK supports the following input levels: LVPECL, CML, on the outputs during asynchronous assertion/deassertion of the OE SSTL pin. The 8534-01s low output and part-to-part skew characteristics Maximum output frequency: 500MHz make it ideal for workstation, server, and other high performance clock distribution applications. Output skew: 100ps (maximum) Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input Additive phase jitter, RMS): 0.15ps (typical) Full 3.3V supply mode 0C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Pullup CLK SEL Pulldown CLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 22 Pullup/Pulldown 0 VCCO 1 48 VCCO nCLK Q0:Q21 22 nc 2 47 Q7 Pulldown nQ0:nQ21 PCLK nc nQ7 1 3 46 Pullup/Pulldown LE nPCLK VCC Q8 4 45 Q nQ8 Pullup CLK 5 44 OE D 6 Q9 nCLK 43 nQ9 CLK SEL 7 42 Q10 PCLK 8 41 nQ10 nPCLK 9 40 VEE Q11 10 39 nQ11 OE 11 38 nc 12 Q12 37 nc nQ12 13 36 nQ21 Q13 14 35 nQ13 Q21 15 34 VCCO VCCO 16 33 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 22 8534-01 64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View 2015 Integrated Device Technology, Inc. 1 Revision C, December 1, 20158534-01 Datasheet Pin Descriptions and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 16, 17, 32, V Power Output supply pins for LVPECL outputs. CCO 33, 48, 49, 64 2, 3, 12, 13 nc Unused No connect. Power Core supply pin for LVPECL outputs. 4V CC 5 CLK Input Pulldown Non-inverting differential clock input. Pullup/ 2 6 nCLK Input Inverting differential clock input. Pulled to / V . 3 CC Pulldown Clock select input. When HIGH, selects PCLK, nPCLK inputs. 7 CLK SEL Input Pullup When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 8 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 2 9 nPCLK Input Inverting differential LVPECL clock input. Pulled to / V . 3 CC Pulldown 10 V Power Negative supply pin. EE Output enable. When logic HIGH, the outputs are enabled (default). 11 OE Input Pullup When logic LOW, the outputs are disabled and drive differential low: Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels. 14, 15 nQ21, Q21 Output Differential clock outputs. LVPECL interface Levels. 18, 19 nQ20, Q20 Output Differential clock outputs. LVPECL interface Levels. 20, 21 nQ19, Q19 Output Differential clock outputs. LVPECL interface Levels. 22, 23 nQ18, Q18 Output Differential clock outputs. LVPECL interface Levels. 24, 25 nQ17, Q17 Output Differential clock outputs. LVPECL interface Levels. 26, 27 nQ16, Q16 Output Differential clock outputs. LVPECL interface Levels. 28, 29 nQ15, Q15 Output Differential clock outputs. LVPECL interface Levels. 30, 31 nQ14, Q14 Output Differential clock outputs. LVPECL interface Levels. 34, 35 nQ13, Q13 Output Differential clock outputs. LVPECL interface Levels. 36, 37 nQ12, Q12 Output Differential clock outputs. LVPECL interface Levels. 38, 39 nQ11, Q11 Output Differential clock outputs. LVPECL interface Levels. 40, 41 nQ10, Q10 Output Differential clock outputs. LVPECL interface Levels. 42, 43 nQ9, Q9 Output Differential clock outputs. LVPECL interface Levels. 44, 45 nQ8, Q8 Output Differential clock outputs. LVPECL interface Levels. 46, 47 nQ7, Q7 Output Differential clock outputs. LVPECL interface Levels. 50, 51 nQ6, Q6 Output Differential clock outputs. LVPECL interface Levels. 52, 53 nQ5, Q5 Output Differential clock outputs. LVPECL interface Levels. 54, 55 nQ4, Q4 Output Differential clock outputs. LVPECL interface Levels. 56, 57 nQ3, Q3 Output Differential clock outputs. LVPECL interface Levels. 58, 59 nQ2, Q2 Output Differential clock outputs. LVPECL interface Levels. 60, 61 nQ1, Q1 Output Differential clock outputs. LVPECL interface Levels. 62, 63 nQ0, Q0 Output Differential clock outputs. LVPECL interface Levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2015 Integrated Device Technology, Inc. 2 Revision C, December 1, 2015