LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO- ICS8535I-21 3.3V LVPECL CLOCK GENERATOR General Description Features The ICS8535I-21 is a low skew, high performance Two differential 3.3V LVPECL outputs ICS 1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout Selectable CLK0 or CLK1 inputs for redundant and multiple HiPerClockS buffer and a member of the HiPerClockS family of frequency fanout applications High Performance Clock Solutions from IDT. The CLK0 or CLK1 can accept the following input levels: ICS8535I-21 has two single-ended clock inputs. The LVCMOS or LVTTL single-ended clock input accepts LVCMOS or LVTTL input levels Maximum output frequency: 266MHz and translate them to 3.3V LVPECL levels. The clock enable is Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable Output skew: 20ps (maximum) pin. Part-to-part skew: 300ps (maximum) Guaranteed output and part-to-part skew characteristics make the Propagation delay: 1.6ns (maximum) ICS8535I-21 ideal for those applications demanding well defined Additive phase jitter, RMS: 0.03ps (typical) performance and repeatability. 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup CLK EN V D EE 1 14 V CC Q CLK EN 2 13 Q0 LE nQ0 CLK SEL 3 12 Pulludown CLK0 0 CLK0 4 11 nc Q0 V EE 5 10 Q1 Pulludown nQ0 CLK1 CLK1 6 9 nQ1 1 V CC 7 8 V CC Q1 Pulludown CLK SEL nQ1 ICS8535I-21 14 Lead TSSOP 4.40mm x 5.0mm x 0.925mm package body G Package Top View IDT / ICS 3.3V LVPECL FANOUT BUFFER 1 ICS8535AGI-21 REV. A NOVEMBER 24, 2008ICS8535I-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 5 V Power Negative supply pins. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. 3 CLK SEL Input Pulldown When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels. 4, 6 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 7, 8, 14 V Power Power supply pins. CC 9, 10 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 11 nc Unused No connect. 12, 13 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN IDT / ICS 3.3V LVPECL FANOUT BUFFER 2 ICS8535AGI-21 REV. A NOVEMBER 24, 2008