8535AGI-31LFT Renesas

VCC Low Skew, 1-To-4, ICS8535I-31 Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer General Description Features The ICS8535I-31 is a low skew, high performance Four differential 3.3V LVPECL outputs ICS 1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V Selectable LVCMOS/LVTTL CLK or crystal inputs HiPerClockS LVPECL fanout buffer. The ICS8535I-31 has CLK can accept the following input levels: LVCMOS, LVTTL selectable single ended clock or crystal inputs. The Maximum output frequency: 266MHz single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The output Output skew: 30ps (typical) enable is internally synchronized to eliminate runt pulses on the Part-to-part skew: 200ps (maximum) outputs during asynchronous assertion/deassertion of the clock Propagation delay: 1.75ns (maximum) enable pin. Additive phase jitter, RMS: 0.057ps (typical) Guaranteed output and part-to-part skew characteristics make the Full 3.3V supply mode ICS8535I-31 ideal for those applications demanding well defined -40C to 85C ambient operating temperature performance and repeatability. Replaces the ICS8535I-11 Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram Pin Assignment Pullup CLK EN D Q LE Pulldown CLK V Q0 0 EE 1 20 Q0 2 19 nQ0 CLK EN nQ0 CLK SEL 3 18 VCC XTAL IN CLK 4 17 Q1 1 OSC Q1 nc 5 16 nQ1 nQ1 XTAL OUT XTAL IN 6 15 Q2 XTAL OUT nQ2 7 14 Q2 nQ2 nc 8 13 Pulldown CLK SEL nc Q3 9 12 Q3 V 10 11 nQ3 CC nQ3 ICS8535I-31 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View ICS8535AGI-31 REVISION A JANUARY 27, 2010 1 2010 Integrated Device Technology, Inc.ICS8535I-31 LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follows clock input. 2 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects XTAL inputs 3 CLK SEL Input Pulldown When LOW, selects CLK input. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 5, 8, 9 nc Unused No connect. 6, XTAL IN, Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 7 XTAL OUT 10, 13, 18 V Power Positive supply pins. CC 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS8535AGI-31 REVISION A JANUARY 27, 2010 2 2010 Integrated Device Technology, Inc.