Low Skew, 1-to-6, Crystal Oscillator/LVCMOS- 8536I-33 TO-3.3V, 2.5V LVPECL/LVCMOS Fanout Buffer DATA SHEET GENERAL DESCRIPTION FEATURES The 8536I-33 is a low skew, high performance Three differential LVPECL outputs, and 1-to-6 Crystal Oscillator/LVCMOS-to-3.3V, 2.5V LVPECL/ three single ended LVCMOS outputs LVCMOS fanout buffer. The 8536I-33 has selectable sin- Selectable LVCMOS/LVTTL CLK or crystal inputs gle ended clock or crystal inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translate CLK can accept the following input levels: LVCMOS, LVTTL them to 3.3V LVPECL levels. The output enable is internally Crystal frequency: 25MHz synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Maximum output frequency: 266MHz Guaranteed output and part-to-part skew characteristics make Output skew: 80ps (maximum) the 8536I-33 ideal for those applications demanding well Part-to-part skew: 800ps (maximum) de ned performance and repeatability. Propagation delay: 1.95ns (maximum) Additive phase jitter, RMS: 0.32ps (typical), LVPECL output Full 3.3V or 2.5V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Pullup CLK EN D LE Pulldown CLK LVPECL 0 Q0 25MHz nQ0 XTAL IN Q1 1 OSC nQ1 XTAL OUT Q2 8536I-33 nQ2 Pullup 20-Lead TSSOP CLK SEL 6.5mm x 4.4mm x 0.925mm package body LVCMOS G Package Q3 Top View Q4 Q5 8536I-33 REVISION B 7/10/15 1 8536I-33 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Synchronizing clock enable. When HIGH, clock outputs follows clock input. 1 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ0 output is forced high. LVCMOS / LVTTL interface levels. 2, XTAL IN, Crystal oscillator interface. XTAL IN is the input. Input 3 XTAL OUT XTAL OUT is the output. 4V Power Positive supply pins. CC 5 CLK Input Pulldown Single-ended clock input. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects XTAL inputs. 6 CLK SEL Input Pullup When LOW, selects CLK input. LVCMOS / LVTTL interface levels. 7, 15, V Power Negative supply pin. EE 20 8, 9 Q0, nQ0 Output Differential clock outputs. LVPECL interface levels. 10 V Power Output power supply mode for LVPECL clock outputs. CCO LVPECL 11, 12 Q1, nQ1 Output Differential clock outputs. LVPECL interface levels. 13, 14 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 16, 18, 19 Q3, Q4, Q5 Output Single ended clock outputs. LVCMOS / LVTTL interface levels. 17 V Power Output power supply mode for LVCMOS / LVTTL clock outputs. CCO LVCMOS NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V V = 3.465V 8 pF Power Dissipation CC, CCO LVCMOS C Q3:Q5 PD Capacitance (per output) V V = 2.625V 5 pF CC, CCO LVCMOS R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Q3:Q5 V V = 3.465V 15 CC, CCO LVCMOS R Output Impedance OUT Q3:Q5 V V = 2.625V 20 CC, CCO LVCMOS LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO- 2 REVISION B 7/10/15 3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER