QB1 Low Skew, Dual, 1-to-3, Differential-to-2.5V, ICS853S013I 3.3V LVPECL/ECL Fanout Buffer DATASHEET General Description Features The ICS853S013I is a low skew, high performance dual 1-to-3 Two differential LVPECL/ECL bank outputs Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer. The Two differential LVPECL clock input pairs ICS853S013I operates with a positive or negative power supply at PCLKx, nPCLKx pairs can accept the following 2.5V or 3.3V. Guaranteed output and part-to-part skew differential input levels: LVPECL, LVDS, CML, SSTL characteristics make the ICS853S013I ideal for those clock Output frequency: 2GHz (maximum) distribution applications demanding well defined performance and Translates any single-ended input signal to LVPECL levels with repeatability. resistor bias on nPCLKx input Bank skew: 60ps (maximum) Part-to-part skew: 190ps (maximum) Propagation delay: 460ps (maximum) Additive phase jitter, RMS: 0.05ps (typical) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.8V to -2.375V CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment QA0 QA1 nQA0 1 20 nQA1 QA0 2 19 Pulldown nQA0 PCLKA VCC 3 18 QA2 Pullup/Pulldown nPCLKA QA1 PCLKA 4 17 nQA2 nPCLKA 5 16 VCC nQA1 PCLKB 6 15 QB2 QA2 nPCLKB 7 14 nQB2 VCC 8 13 nQA2 nQB0 9 12 nQB1 QB0 10 11 VEE QB0 Pulldown nQB0 PCLKB ICS853S013I Pullup/Pulldown nPCLKB QB1 20-Lead SOIC nQB1 7.5mm x 12.8mm x 2.3mm package body M Package QB2 Top View nQB2 ICS853S013AMI REVISION A AUGUST 20, 2010 1 2010 Integrated Device Technology, Inc.ICS853S013I Data Sheet LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL interface levels. nQA0, QA0 3, 8, 16 V Power Power supply pins. CC 4 PCLKA Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 5 nPCLKA Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 6 PCLKB Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 7 nPCLKB Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 9, 10 Output Differential output pair. LVPECL interface levels. nQB0, QB0 11 V Power Negative supply pin. EE 12, 13 Output Differential output pair. LVPECL interface levels. nQB1, QB1 14, 15 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 17, 18 Output Differential output pair. LVPECL interface levels. nQA2, QA2 19, 20 Output Differential output pair. LVPECL interface levels. nQA1, QA1 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 75 k PULLDOWN R Pullup/Pulldown Resistors 50 k VCC/2 Function Table Table 3. Clock Input Function Table Inputs Outputs QA 0:2 , nQA 0:2 , PCLKA or PCLKB nPCLKA or nPCLKB QB 0:2 nQB 0:2 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels. ICS853S013AMI REVISION A AUGUST 20, 2010 2 2010 Integrated Device Technology, Inc.