VBB1 4:1, Differential-To-3.3V, 2.5V 853S057 LVPECL/ECL Clock Data Multiplexer DA TA SH E E T Description Features The 853S057 is a 4:1 Differential-to-3.3V or 2.5V LVPECL/ECL High speed 4:1 differential multiplexer Clock/Data Multiplexer which can operate up to 3GHz. The 853S057 One differential 3.3V, 2.5V LVPECL/ECL output has 4 differential selectable clock input pairs. The CLK, nCLK input Four differential CLKx, nCLKx input pairs pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully Differential CLKx, nCLKx pairs can accept the following interface differential architecture and low propagation delay make it ideal for levels: LVPECL, LVDS, CML, SSTL use in clock distribution circuits. The multiplexer select control inputs Maximum input/output frequency: 3GHz have ECL/LVPECL interface levels. The select pins have internal pull-down resistors. Additive phase jitter, RMS at 622.08MHz: 0.073ps (typical) Part-to-part skew: 250ps (maximum) Propagation delay: 615ps (maximum) LVPECL mode operating voltage supply range: V = 2.375V to 3.465V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.465V to -2.375V CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages Block Diagram Pin Assignment V 1 20 VCC Pulldown CC CLK0 2 19 SEL1 Pulldown 0 0 CLK0 nCLK0 (default) nCLK0 3 18 SEL0 Pulldown CLK1 4 17 CLK1 VCC 0 1 Pulldown nCLK1 nCLK1 5 16 Q Q CLK2 6 15 nQ nQ Pulldown CLK2 nCLK2 VCC 7 14 Pulldown 1 0 nCLK2 CLK3 8 13 nCLK3 9 12 VBB2 Pulldown CLK3 V EE 10 11 VEE Pulldown 1 1 nCLK3 853S057 Pulldown SEL1 20-Lead TSSOP Pulldown SEL0 6.5mm x 4.4mm x 0.925mm V BB1 package body V BB2 G Package Top View 853S057AGI AUGUST 13, 2021 1 2021 Renesas Electronics Corporation853S057 Datasheet 4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1, 14, 17, 20 V Power Positive supply pins. CC 2 CLK0 Input Pulldown Non-inverting differential clock input. 3 nCLK0 Input Pulldown Inverting differential clock input. 4 CLK1 Input Pulldown Non-inverting differential clock input. 5 nCLK1 Input Pulldown Inverting differential clock input. 6 CLK2 Input Pulldown Non-inverting differential clock input. 7 nCLK2 Input Pulldown Inverting differential clock input. 8 CLK3 Input Pulldown Non-inverting differential clock input. 9 nCLK3 Input Pulldown Inverting differential clock input. 10, 11 V Power Negative supply pins. EE 12, 13 V V Output ECL reference outputs. BB2, BB1 15, 16 nQ, Q Output Differential output pair. ECL/LVPECL interface levels. 18, 19 Input Pulldown Clock select inputs. ECL/LVPECL or LVCMOS interface levels. SEL0, SEL1 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN Function Tables Table 3. Control Input Function Table Control Inputs Clock Out SEL1 SEL0 Q, nQ 0 0 (default) CLK0, nCLK0 0 1 CLK1, nCLK1 1 0 CLK2, nCLK2 1 1 CLK3, nCLK3 853S057AGI AUGUST 13, 2021 2 2021 Renesas Electronics Corporation