Low Skew, 1-to-10, 853S111AI Differential-to-LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The 853S111AI is a low skew, high performance 1-to-10 Ten differential 2.5V, 3.3V LVPECL/ECL outputs Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The Two selectable differential input pairs 853S111AI is characterized to operate from either a 2.5V or a 3.3V PCLKx, nPCLKx pairs can accept the following power supply. Guaranteed output and part-to-part skew differential input levels: LVPECL, LVDS, SSTL, CML characteristics make the 853S111AI ideal for those clock distribution Maximum output frequency: 2.5GHz applications demanding well defined performance and repeatability. Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input Output skew: 55ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 780ps (maximum) Additive phase jitter, RMS: 0.07ps (typical) LVPECL mode operating voltage supply range: V = 2.375V to 3.465V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.465V to -2.375V CC EE -40C to 85C ambient operating temperature Available lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown PCLK0 0 Pullup/Pulldown Q0 nPCLK0 24 23 22 21 20 19 18 17 nQ0 Pulldown PCLK1 VCCO 25 1 16 VCCO Pullup/Pulldown nPCLK1 Q1 26 nQ2 15 Q7 nQ1 Pulldown Q2 27 nQ7 CLK SEL 14 Q2 28 Q8 nQ1 13 V BB nQ2 Q1 nQ8 29 12 nQ3 nQ0 30 Q9 11 nQ3 Q0 31 10 nQ9 Q4 VCCO 32 9 VCCO 1 2 3 4 5 6 7 8 nQ4 Q5 nQ5 Q6 853S111AI nQ6 32-Lead LQFP Q7 7mm x 7mm x 1.4mm package body nQ7 Y Package nQ8 Top View nQ8 Q9 nQ9 853S111AI Rev A 6/30/15 1 2015 Integrated Device Technology, Inc. VCC Q3 CLK SEL nQ3 Q4 PCLK0 nPCLK0 nQ4 VBB Q5 PCLK1 nQ5 nPCLK1 Q6 VEE nQ6853S111AI DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1V Power Positive supply pin. CC Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, 2 CLK SEL Input Pulldown selects PCLK0, nPCLK0 inputs. LVPECL interface levels. Also accepts standard LVCMOS/LVTTL input levels. 3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 4 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 5V Output Bias voltage to be connected for single-ended LVPECL input. BB 6 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 7 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 8V Power Negative supply pin. EE 9, 16, 25, 32 V Power Output supply pins. CCO 10, 11 Output Differential output pair. LVPECL/ECL interface levels. nQ9, Q9 12, 13 nQ8, Q8 Output Differential output pair. LVPECL/ECL interface levels. 14, 15 Output Differential output pair. LVPECL/ECL interface levels. nQ7, Q7 17, 18 Output Differential output pair. LVPECL/ECL interface levels. nQ6, Q6 19, 20 nQ5, Q5 Output Differential output pair. LVPECL/ECL interface levels. 21, 22 Output Differential output pair. LVPECL/ECL interface levels. nQ4, Q4 23, 24 Output Differential output pair. LVPECL/ECL interface levels. nQ3, Q3 26, 27 nQ2, Q2 Output Differential output pair. LVPECL/ECL interface levels. 28, 29 Output Differential output pair. LVPECL/ECL interface levels. nQ1, Q1 30, 31 Output Differential output pair. LVPECL/ECL interface levels. nQ0, Q0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 75 k PULLDOWN R Pullup/Pulldown Resistors 50 k VCC/2 Rev A 6/30/15 2 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER