VCC Q8 nQ8 Q9 nQ9 VCC Q10 nQ10 LOW SKEW, 1-TO-12, DIFFERENTIAL-TO- ICS853S12I 3.3V, 2.5V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853S12I is a low skew, 1-to-12 Differential- Twelve differential 3.3V, 2.5V LVPECL outputs ICS to-3.3V, 2.5V LVPECL Fanout Buffer and a member PCLK, nPCLK input pair HiPerClockS of the HiPerClockS family of High Performance Clock Solutions from IDT. The PCLK, nPCLK pair PCLK, nPCLK pair can accept the following differential accepts LVPECL, CML, and SSTL differential input input levels: LVPECL, CML, SSTL levels. The high gain differential amplifier accepts peak-to-peak Maximum output frequency: 1.5GHz input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. Translates any single-ended input signal to 2.5V or 3.3V LVPECL levels with a resistor bias on nPCLK input Guaranteed output and part-to-part skew characteristics make the ICS853S12I ideal for those clock distribution applications Additive phase jitter, RMS: 0.06ps (typical) demanding well defined performance and repeatability. Output skew: 50ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 680ps (maximum) Full 3.3V or 2.5V operating supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Pulldown PCLK Pullup/Pulldown nPCLK 32 31 30 29 28 27 26 25 Q11 24 nQ7 1 Q11 Q0 nQ11 2 23 Q7 nQ11 nQ0 VEE 3 ICS853S12I 22 nQ6 Q10 Q1 32-Lead VFQFN PCLK 4 21 Q6 nQ10 nQ1 5mm x 5mm x 0.925mm nPCLK 5 20 nQ5 Q9 package body Q2 VEE 6 19 Q5 nQ9 nQ2 K Package Q0 7 18 nQ4 Top View Q8 Q3 nQ0 8 Q4 nQ8 17 nQ3 Q4 Q7 9 10 11 12 13 14 15 16 nQ7 nQ4 Q6 Q5 nQ6 nQ5 IDT / ICS LVPECL FANOUT BUFFER 1 ICS853S12AKI REV. A MAY 21, 2008 Q1 nQ1 VCC Q2 nQ2 Q3 nQ3 VCCICS853S12I LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 11, 2Qt11, nQ1O.utpu Differential output pair. LVPECL interface levels 3V, 6 P.ower Negative supply pins EE 4KPtCL InnpuP.ulldow Non-inverting differential clock input Pullup/ 5KntPCL Inpu Inverting differential clock input. Pulldown 70, 8 Qt0, nQO.utpu Differential output pair. LVPECL interface levels 91, 10 Qt1, nQO.utpu Differential output pair. LVPECL interface levels 1V1, 16, 25, 30 P.ower Positive supply pins CC 122, 13Qt2, nQO.utpu Differential output pair. LVPECL interface levels 134, 15Qt3, nQO.utpu Differential output pair. LVPECL interface levels 147, 18Qt4, nQO.utpu Differential output pair. LVPECL interface levels 159, 20Qt5, nQO.utpu Differential output pair. LVPECL interface levels. 261, 22Qt6, nQO.utpu Differential output pair. LVPECL interface levels 273, 24Qt7, nQO.utpu Differential output pair. LVPECL interface levels 298, 29Qt9, nQO.utpu Differential output pair. LVPECL interface levels 286, 27Qt8, nQO.utpu Differential output pair. LVPECL interface levels 301, 32Qt10, nQ1O.utpu Differential output pair. LVPECL interface levels NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 2Fp IN R Input Pullup Resistor 5k0 PULLUP R Input Pulldown Resistor 5k0 PULLDOWN TABLE 3. CLOCK INPUT FUNCTION TABLE Isnputs Output Iynput to Output Mode Polarit PKCLKn1PCLQ10:Q1 nQ0:nQ1 01 LHOWHlIGDgifferential to Differentia Non Invertin 10 HWIGHLlODgifferential to Differentia Non Invertin 01BWiased NOTELHOHlIGSgingle Ended to Differentia Non Invertin 11BHiased NOTEHWIGLlOSgingle Ended to Differentia Non Invertin B0iased NOTE 1 HWIGHLlOSgingle Ended to Differentia Invertin B1iased NOTE 1 LHOWHlIGSgingle Ended to Differentia Invertin NOTE 1: Please refer to the Application InformationWiring the Differential Input to Accept Single Ended Level. IDT / ICS LVPECL FANOUT BUFFER 2 ICS853S12AKI REV. A MAY 21, 2008