12:2, Differential-to-3.3V, 2.5V 853S202 LVPECL Multiplexer Datasheet Description Features The 853S202 is a 12:2 Differential-to-LVPECL Clock Multiplexer High speed 12.2 differential multiplexer which can operate up to 3GHz. The 853S202 has twelve select- Two differential 3.3V or 2.5V LVPECL outputs able differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input Twelve selectable differential clock or data inputs pairs can accept LVPECL or LVDS levels. The fully differential ar- CLKx, nCLKx pairs can accept the following differential input chitecture and low propagation delay make it ideal for use in clock levels: LVPECL, LVDS distribution circuits. Maximum output frequency: 3GHz Translates any single ended input signal to LVPECL levels with resistor bias on nCLKx input Propagation delay: 1.15ns (maximum) Input skew: 150ps (maximum) Output skew: 50ps (maximum) Part-to-part skew: 250ps (maximum) Additive phase jitter, RMS: 0.114ps (typical) 155.52MHz, 3.3V Full 3.3V or 2.5V operating supply mode -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignments 4 Pulldown SELA 3:0 Pulldown CLK0 Pullup/Pulldown nCLK0 48 47 46 45 44 43 42 41 40 39 38 37 Pulldown CLK1 CLK2 1 36 CLK9 Pullup/Pulldown nCLK1 nCLK2 2 35 nCLK9 Pulldown SELA 0 3 34 SELB 0 CLK2 853S202 ICS853S202I Pullup/Pulldown SELA 1 4 33 SELB 1 nCLK2 48-Pin LQFP QA V 5 32 V CC CC Pulldown CLK3 nQA QA 6 7mm x 7mm x 1.4mm 31 QB Pullup/Pulldown nCLK3 Pullup nQA 7 30 nQB OEA package body Pulldown CLK4 V 8 29 V EE EE Pullup/Pulldown Y Package nCLK4 SELA 2 9 28 SELB 2 Top View SELA 3 10 27 SELB 3 Pulldown CLK5 Pullup/Pulldown CLK3 11 26 CLK8 nCLK5 nCLK3 12 25 nCLK8 13 14 15 16 17 18 19 20 21 22 23 24 Pulldown CLK6 Pullup/Pulldown nCLK6 Pulldown CLK7 Pullup/Pulldown nCLK7 Pulldown CLK8 QB Pullup/Pulldown nCLK8 nQB Pulldown Pullup CLK9 OEB Pullup/Pulldown nCLK9 Pulldown CLK10 Pullup/Pulldown nCLK10 Pulldown CLK11 Pullup/Pulldown nCLK11 4 Pulldown SELB 3:0 2018 Integrated Device Technology, Inc. 1 July 23, 2018 nCLK4 nCLK1 CLK4 CLK1 V V EE EE nCLK5 nCLK0 CLK5 CLK0 V V CC CC OEA OEB CLK6 CLK11 nCLK6 nCLK11 V V EE EE CLK7 CLK10 nCLK7 nCLK10853S202 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 CLK2 Input Pulldown Non-inverting differential clock input. Pullup/ 2nCLK2 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 3, SELA 0, 4, SELA 1, Clock select pins for Bank A output pair. See Control Input Function Table. Input Pulldown 9, SELA 2, LVCMOS/LVTTL interface levels. See Table 3B. 10 SELA 3 5, 18, 32, 43 V Power Power supply pins. CC 6, 7 QA, nQA Output Clock outputs. LVDS interface levels. 8, 15, 22, 29, V Power Power supply ground. EE 39, 46 11 CLK3 Input Pulldown Non-inverting differential clock input. Pullup/ 12 nCLK3 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown Pullup/ 13 nCLK4 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 14 CLK4 Input Pulldown Non-inverting differential clock input. Pullup/ 16 nCLK5 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 17 CLK5 Input Pulldown Non-inverting differential clock input. Output enable pin. Controls enabling and disabling of QA, nQA output pair. 19 OEA Input Pullup LVCMOS/LVTTL interface levels. 20 CLK6 Input Pulldown Non-inverting differential clock input. Pullup/ 21 nCLK6 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 23 CLK7 Input Pulldown Non-inverting differential clock input. Pullup/ 24 nCLK7 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown Pullup/ 25 nCLK8 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 26 CLK8 Input Pulldown Non-inverting differential clock input. 27, SELB 3, 28, SELB 2, Clock select pins for Bank B output pair. See Control Input Function Table. Input Pulldown 33, SELB 1, LVCMOS/LVTTL interface levels. See Table 3C. 34 SELB 0 30, 31 nQB, QB Output Clock outputs. LVDS interface levels. Pullup/ 35 nCLK9 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 36 CLK9 Input Pulldown Non-inverting differential clock input. Pullup/ 37 nCLK10 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 38 CLK10 Input Pulldown Non-inverting differential clock input. 2018 Integrated Device Technology, Inc. 2 July 23, 2018