nQ3 Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS 854105I Fanout Buffer Datasheet General Description Features The 854105I is a low skew, high performance 1-to-4 Four differential LVDS output pairs LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage One single-ended LVCMOS/LVTTL input Differential Signaling (LVDS), the 854105I provides a low power, low CLK can accept the following input levels: LVCMOS, LVTTL noise solution for distributing clock signals over controlled Maximum output frequency: 250MHz impedances of 100. The 854105I accepts an LVCMOS/LVTTL input level and translates it to LVDS output levels. Translates single-ended input signals to LVDS levels Guaranteed output and part-to-part skew characteristics make the Additive phase jitter, RMS: 0.16ps (typical) 854105I ideal for those applications demanding well defined Output skew: 72ps (maximum) performance and repeatability. Part-to-part skew: 350ps (maximum) Propagation delay: 1.75ns (maximum) 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 OE0 1 16 Q0 OE1 2 15 nQ0 nQ0 OE2 3 14 Q1 Pullup OE0 V DD 4 13 nQ1 5 12 Q2 GND Q1 CLK 6 11 nQ2 nc 7 10 Q3 nQ1 OE3 8 9 Pullup OE1 Pulldown CLK 854105I Q2 16-Lead TSSOP nQ2 4.4mm x 5.0mm x 0.925mm package body Pullup OE2 G Package Top View Q3 nQ3 Pullup OE3 2016 Integrated Device Technology, Inc. 1 Revision B, February 23, 2016854105I Datasheet Pin Description and Pin Characteristics Table 1. Pin Descriptions Number Name Type Description 1 OE0 Input Pullup Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL interface levels. 2 OE1 Input Pullup Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL interface levels. 3 OE2 Input Pullup Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL interface levels. 4V Power Positive supply pin. DD 5 GND Power Power supply ground. 6 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 7 nc Unused No connect. 8 OE3 Input Pullup Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL interface levels. 9, 10 nQ3, Q3 Output Differential output pair. LVDS interface levels. 11, 12 nQ2, Q2 Output Differential output pair. LVDS interface levels. 13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Function Table Table 3. Output Enable Function Table Inputs Outputs OE 3:0 Q 3:0 , nQ 3:0 0 High-Impedance 1 Active (default) 2016 Integrated Device Technology, Inc. 2 Revision B, February 23, 2016