2.5V Differential LVDS Clock Buffer ICS854110I DATA SHEET General Description Features The ICS854110I is a high-performance differential LVDS clock fanout Two differential input reference clocks buffer. The device is designed for signal fanout of high-frequency, low Differential pair can accept the following differential input levels: phase-noise clock signals. The selected differential input signal is LVPECL, LVDS distributed to ten differential LVDS outputs. The ICS854110I is Ten LVDS outputs characterized to operate from a 2.5V power supply. Guaranteed Maximum clock frequency: 200MHz output-to-output and part-to-part skew characteristics make the Output slew rate control ICS854110I ideal for those clock distribution applications demanding well-defined performance and repeatability. The device offers an Fail-safe differential inputs output slew rate control with four pre-set output transition times to LVCMOS interface levels for all control inputs solve crosstalk and EMI problems in complex board designs. A Output skew: 260ps (maximum), for fastest slew rate setting of fail-safe input design forces the outputs to a defined state if 0.650 V/ns differential clock inputs are open or shorted, see Table 3D. Part-to-part skew: 1.2ns (maximum) Full 2.5V supply voltage Lead-free (RoHS 6) 32-Lead VFQFN and 32-Lead LQFP package -40C to 85C ambient operating temperature Pin Assignments Block Diagram Q0 nQ0 32 31 30 29 28 27 26 25 1 ISET 24 Q3 Q1 854110AKI CLK SEL 2 23 nQ3 nQ1 32-Lead VFQFN 3 Q4 CLK0 22 CLK0 0 5mm x 5mm x 0.925mm f nCLK0 REF nQ4 nCLK0 4 21 Q2 package body nQ2 GND 5 20 Q5 K package CLK1 1 Top View CLK1 6 nQ5 19 nCLK1 Q3 nCLK1 7 Q6 18 nQ3 Pulldown CLK SEL nOE 8 nQ6 17 9 10 11 12 13 14 15 16 Q4 nQ4 Q5 ISET Slew-Rate nQ5 Control Q6 32 31 30 29 28 27 26 25 R SET nQ6 ISET 1 Q3 24 CLK SEL 2 23 nQ3 854110AYI Q7 32-Lead LQFP CLK0 3 22 Q4 GND nQ7 7mm x 7mm x 1.4mm nQ4 nCLK0 4 21 package body Q8 GND Q5 5 20 Y package nQ8 Pulldown CLK1 6 19 nQ5 nOE Top View nCLK1 7 Q6 18 Q9 nQ9 nOE 8 nQ6 17 9 10 11 12 13 14 15 16 ICS854110AKI REVISION B JANUARY 27, 2011 1 2011 Integrated Device Technology, Inc. GND VDD GND VDD nQ9 Q0 Q0 nQ9 Q9 nQ0 nQ0 Q9 nQ8 Q1 Q1 nQ8 nQ1 Q8 nQ1 Q8 nQ7 Q2 nQ7 Q2 nQ2 Q7 Q7 nQ2 VDD GND GND VDDICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Table 1. Pin Descriptions Number Name Type Description An external fixed resistor (RSET) from this pin to ground is needed to provide a 1 ISET reference current for setting the slew rate of the differential outputs Q 0:9 , nQ 0:9 . See Table 3C for function. 2 CLK SEL Input Pulldown Input clock select. See Table 3A for function. LVCMOS/LVTTL interface levels. 3 CLK0 Input Non-inverting clock/data input 0. 4 nCLK0 Input Inverting differential clock input 0. 5, 9, 25 GND Power Power supply ground. 6 CLK1 Input Non-inverting clock/data input 1. 7 nCLK1 Input Inverting differential clock input 1. 8 nOE Input Pulldown Output enable. See Table 3B for function. LVCMOS/LVTTL interface levels. 10, 11 nQ9, Q9 Output Differential output pair 9. LVDS interface levels. 12, 13 nQ8, Q8 Output Differential output pair 8. LVDS interface levels. 14, 15 nQ7, Q7 Output Differential output pair 7. LVDS interface levels. 16, 32 V Power Power supply pins. DD 17, 18 nQ6, Q6 Output Differential output pair 6. LVDS interface levels. 19, 20 nQ5, Q5 Output Differential output pair 5. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair 4. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair 3. LVDS interface levels. 26, 27 nQ2, Q2 Output Differential output pair 2. LVDS interface levels. 28, 29 nQ1, Q1 Output Differential output pair 1. LVDS interface levels. 30, 31 nQ0, Q0 Output Differential output pair 0. LVDS interface levels. NOTE: Pulldown refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN ICS854110AKI REVISION B JANUARY 27, 2011 2 2011 Integrated Device Technology, Inc.