Low Skew, 1-to-5, ICS854S015I-01 Differential-to-LVDS/LVPECL Fanout Buffer DATA SHEET General Description Features The ICS854S015I-01 is a low skew, high performance 1-to-5, 2.5V, Five differential LVPECL or LVDS output pairs 3.3V Differential-to-LVPECL/LVDS Fanout Buffer. The Two differential clock input pairs ICS854S015I-01 has two selectable differential clock inputs. CLK, nCLK pair can accept the following differential input levels: Guaranteed output and part-to-part skew characteristics make the LVDS, LVPECL, LVHSTL, HCSL ICS854S015I-01 ideal for those applications demanding well defined PCLK, nPCLK can accept the following input levels: LVPECL, performance and repeatability. LVDS, CML Either CLK or PCLK inputs can be configured to accept single-ended inputs Maximum output frequency: 2GHz Additive phase jitter, RMS: 0.065ps (maximum), 3.3V, 156.25MHz, 12kHz 5MHz) Output Skew: 55ps (maximum) Propagation delay: 570ps (typical) 3.3V Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown nCLK EN D Q LE Pulldown PCLK 24 23 22 21 20 19 0 Pullup/Pulldown nPCLK Q0 PCLK 1 18 nQ1 nQ0 2 VCC Pulldown nPCLK 17 CLK 1 Pullup/Pulldown nCLK Q1 3 VCC 16 VEE nQ1 4 15 Q2 VCC TAP Pulldown CLK SEL Q2 nQ2 CLK 5 14 nQ2 Q3 nCLK 6 13 7 8 9 10 11 12 V Q3 CC TAP nQ3 Q4 nQ4 ICS854S015I-01 Pulldown SEL OUT 24-Lead VFQFN 4mm x 4mm x 0.925mm package body K Package Top View ICS854S015CKI-01 REVISION A OCTOBER 4, 2011 1 2011 Integrated Device Technology, Inc. SEL OUT nCLK EN nc CLK SEL VCC VEE Q0 nQ4 Q4 nQ0 Q1 nQ3ICS854S015I-01 Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 2 nPCLK Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 3, 9, 17 V Power Positive supply pins. CC 4V Power Power supply pin. See Table 3C. CC TAP 5 CLK Input Pulldown Non-inverting differential clock input. Pullup/ 6 nCLK Input Inverting differential clock input. V /2 default when left floating. CC Pulldown Output select pin. When LOW, selects LVDS output levels. When HIGH, selects 7 SEL OUT Input Pulldown LVPECL output levels. See Table 3. LVCMOS/LVTTL interface levels. 8 nc Unused No-connect. 10, 11 nQ4, Q4 Output Differential output pair. LVDS or LVPECL interface levels. 12, 13 nQ3, Q3 Output Differential output pair. LVDS or LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVDS or LVPECL interface levels. 16, 22 V Power Negative supply pins. EE 18, 19 nQ1, Q1 Output Differential output pair. LVDS or LVPECL interface levels. 20, 21 nQ0, Q0 Output Differential output pair. LVDS or LVPECL interface levels. Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, selects 23 CLK SEL Input Pulldown PCLK, nPCLK inputs. LVTTL / LVCMOS interface levels. Synchronizing clock enable. When LOW, clock outputs follow clock input. 24 nCLK EN Input Pulldown When HIGH, Qx outputs are forced low, nQx outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pulldown Resistor 50 k PULLDOWN R /2 Pullup/Pulldown Resistor 50 k VCC ICS854S015CKI-01 REVISION A OCTOBER 4, 2011 2 2011 Integrated Device Technology, Inc.