2:1 Differential-to-LVDS Multiplexer ICS854S01I DATASHEET General Description Features The ICS854S01I is a high performance 2:1 Differential-to-LVDS 2:1 LVDS MUX Multiplexer. The ICS854S01I can also perform differential translation One LVDS output pair because the differential inputs accept LVPECL, LVDS or CML levels. Two differential clock inputs can accept: LVPECL, LVDS, CML The ICS854S01I is packaged in a small 3mm x 3mm 16 VFQFN Maximum input/output frequency: 2.5GHz package, making it ideal for use on space constrained boards. Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 RMS additive phase jitter: 0.06ps (typical) Propagation delay: 600ps (maximum) Part-to-part skew: 350ps (maximum) Full 3.3V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown PCLK0 0 Pullup/Pulldown nPCLK0 Q 16 15 14 13 nQ 1 PCLK0 12 GND Pulldown PCLK1 Pullup/Pulldown 1 nPCLK0 2 11 Q nPCLK1 PCLK1 3 10 nQ nPCLK1 4 9 GND Pulldown CLK SEL 5 6 7 8 ICS854S01I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View ICS854S01AKI June 15, 2017 1 2017 Integrated Device Technology, Inc. RESERVED nc CLK SEL GND nc GND VDD VDDICS854S01I Datasheet 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1 PCLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 2 nPCLK0 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 3 PCLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 4 nPCLK1 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 5 RESERVED Reserve Reserve pin. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When 6 CLK SEL Input Pulldown LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. 7, 16 nc Unused No connects. 8, 13 V Power Power supply pins. DD 9, 12, 14, 15 GND Power Power supply ground. 10, 11 nQ, Q Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2 pF C IN Input Pullup Resistor 37 k R PULLUP R Input Pulldown Resistor 37 k PULLDOWN Function Tables Table 3. Control Input Function Table CLK SEL PCLK Selected 0 PCLK0, nPCLK0 1 PCLK1, nPCLK1 ICS854S01AKI June 15, 2017 2 2017 Integrated Device Technology, Inc.