ICS854S054I 4:1 Differential-to-LVDS Clock Multiplexer DATA SHEET General Description Features The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer High speed 4:1 differential multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable One differential LVDS output pair differential clock inputs. The PCLK, nPCLK input pairs can accept Four selectable differential PCLK, nPCLK input pairs LVPECL, LVDS or CML levels. The fully differential architecture and PCLKx, nPCLKx pairs can accept the following differential low propagation delay make it ideal for use in clock distribution input levels: LVPECL, LVDS, CML circuits. The select pins have internal pulldown resistors. The SEL1 Maximum output frequency: 2.5GHz pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects Translates any single ended input signal to LVDS levels with PCLK0, nPCLK0). resistor bias on nPCLKx input Additive phase jitter, RMS: 0.147ps (typical) Part-to-part skew: 300ps (maximum) Propagation delay: 700ps (maximum) Supply voltage range: 3.135V to 3.465V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment PCLK0 1 16 V DD nPCLK0 2 15 Q PCLK1 3 14 nQ nPCLK1 4 13 GND Pulldown PCLK0 V 5 12 nPCLK3 DD 00 (default) Pullup/Pulldown SEL0 6 11 PCLK3 nPCLK0 SEL1 7 10 nPCLK2 GND 8 9 PCLK2 Pulldown PCLK1 ICS854S054I 01 Pullup/Pulldown nPCLK1 16-Lead TSSOP Q 5.0mm x 4.4mm x 0.92mm package body Pulldown PCLK2 nQ G Package 10 Pullup/Pulldown nPCLK2 Top View Pulldown PCLK3 11 Pullup/Pulldown nPCLK3 Pulldown SEL1 Pulldown SEL0 ICS854S054AGI REVISION A SEPTEMBER 28, 2012 1 2012 Integrated Device Technology, Inc.ICS854S054I Data Sheet 4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1 PCLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 2 nPCLK0 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 3 PCLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 4 nPCLK1 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 5, 16 V Power Positive supply pins. DD 6, 7 SEL0, SEL1 Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. 9 PCLK2 Input Pulldown Non-inverting differential clock input. Pullup/ 10 nPCLK2 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 11 PCLK3 Input Pulldown Non-inverting differential clock input. Pullup/ 12 nPCLK3 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 8, 13 GND Power Power supply ground. 14, 15 nQ, Q Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2 pF C IN R Pulldown Resistor 75 k PULLDOWN R /2 RPullup/Pulldown Resistor 50 k VDD Table 3. Clock Input Function Table Inputs Outputs SEL1 SEL0 Q nQ 0 0 PCLK0 nPCLK0 0 1 PCLK1 nPCLK1 1 0 PCLK2 nPCLK2 1 1 PCLK3 nPCLK3 ICS854S054AGI REVISION A SEPTEMBER 28, 2012 2 2012 Integrated Device Technology, Inc.