Dual 2:1, 1:2 Differential-to-LVDS ICS854S54I-01 Multiplexer Datasheet Description Features The ICS854S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer Dual 2:1, 1:2 MUX allows one of two inputs to be selected onto one output pin and the Three LVDS output pairs 1:2 MUX switches one input to both outputs. This device may be Three differential clock inputs can accept: LVPECL, LVDS, CML useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit Loopback test mode available and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop Maximum output frequency: 2.5GHz back testing and allows the output of a PHY transmit pair to be routed Propagation delay: 600ps (maximum) to the PHY input pair. For examples, please refer to the Application Part-to-part skew: 300ps (maximum) Information section of the data sheet. Additive phase jitter, RMS: 0.031ps (typical) The ICS854S54I-01 is optimized for applications requiring very high Full 2.5V supply mode performance and has a maximum operating frequency of 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, -40C to 85C ambient operating temperature making it ideal for use on space-constrained boards. Available in lead-free (RoHS 6) package Pin Assignment Block Diagram SELB 16 15 14 13 1 QA0 12 INA0 2 11 nQA0 nINA0 INA0 3 10 QA1 INA1 nINA0 nQA1 4 nINA1 9 5 6 7 8 INB LOOP0 0 nINB QA0 ICS854S54I-01 nQA0 16-Lead VFQFN 1 0 3mm x 3mm x 0.925mm package body QB Top View nQB INA1 1 nINA1 LOOP1 QA1 nQA1 SELA ICS854S54I-01 July 17, 2017 1 2017 Integrated Device Technology, Inc. Pulldown Pulldown INB QB nINB nQB SELB SELA GND VDDICS854S54I-01 Datasheet DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1, 2 QA0, nQA0 Output Differential output pair. LVDS interface levels. 3, 4 QA1, nQA1 Output Differential output pair. LVDS interface levels. 5 INB Input Pulldown Non-inverting differential clock input. Pullup/ 6 nINB Input Inverting differential clock input. V /2 default when left floating. DD Pulldown Select pin for QAx outputs. When HIGH, selects same inputs used for QB output. 7 SELB Input Pulldown When LOW, selects INB input. LVCMOS/LVTTL interface levels. 8 GND Power Power supply ground. Pullup/ 9 nINA1 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 10 INA1 Input Pulldown Non-inverting differential clock input. Pullup/ 11 nINA0 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 12 INA0 Input Pulldown Non-inverting differential clock input. 13 V Power Power supply pin. DD Select pin for QB outputs. When HIGH, selects INA1 input. 14 SELA Input Pulldown When LOW, selects INA0 input. LVCMOS/LVTTL interface levels. 15, 16 nQB, QB Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 37.5 k PULLUP R Input Pulldown Resistor 37.5 k PULLDOWN Function Tables Table 3. Control Input Function Table Control Inputs SELA SELB Mode 0 0 LOOP0 selected (default) 1 0 LOOP1 selected 0 1 Loopback mode: LOOP0 1 1 Loopback mode: LOOP1 ICS854S54I-01 July 17, 2017 2 2017 Integrated Device Technology, Inc.