nQB0 SEL OUT nPCLK2 4:4 Differential-to-LVPECL/LVDS ICS859S0424I Clock Multiplexer DATA SHEET General Description Features The ICS859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock High speed 4:1 differential multiplexer with a 1:4 fanout buffer Multiplexer which can operate up to 3GHz. The outputs for this Four programmable differential LVPECL or LVDS output pairs device can either be programmed to give LVPECL or LVDS levels. Four selectable differential PCLKx, nPCLKx input pairs The ICS859S0424I has four selectable differential PCLKx, nPCLKx PCLKx, nPCLKx pairs can accept the following differential clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, input levels: LVPECL, LVDS, CML LVDS or CML levels. The fully differential architecture and low Maximum output frequency: 3GHz propagation delay make it ideal for use in clock distribution circuits. Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx inputs Part-to-part skew: 100ps (maximum) Propagation delay: 555ps (typical) 3.3V Additive phase jitter, RMS: 0.22ps (typical) 3.3V Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup OEA CLK SEL0 1 24 VCC Pulldown 2 23 VEE CLK SEL0 CLK SEL1 PCLK0 3 22 QA0 Pulldown CLK SEL1 nPCLK0 4 21 nQA0 PCLK1 5 20 QA1 nPCLK1 6 19 nQA1 Pulldown QA0 PCLK0 PCLK2 7 18 QB0 Pullup/Pulldown 0 0 nPCLK0 nQA0 8 17 9 QB1 PCLK3 16 Pulldown QA1 PCLK1 nPCLK3 10 15 nQB1 Pullup/Pulldown 0 1 nPCLK1 nQA1 OEA 11 14 VCC TAP OEB 12 13 QB0 Pulldown PCLK2 1 0 Pullup/Pulldown nPCLK2 nQB0 ICS859S0424I QB1 24-Lead TSSOP Pulldown PCLK3 1 1 Pullup/Pulldown nQB1 4.4mm x 7.8mm x 0.925mm package body nPCLK3 G Package Top View Pullup OEB Pullup SEL OUT ICS859S0424BGI REVISION A OCTOBER 12, 2011 1 2011 Integrated Device Technology, Inc.ICS859S0424I Data Sheet 4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER Table 2. Pin Descriptions Number Name Type Description 1, CLK SEL0, Input Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels. 2 CLK SEL1 3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 4 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 5 PCLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 6 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 7 PCLK2 Input Pulldown Non-inverting differential clock input. Pullup/ 8 nPCLK2 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 9 PCLK3 Input Pulldown Non-inverting differential clock input. Pullup/ 10 nPCLK3 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown Output enable pin for Bank A outputs. See Table 4B. 11 OEA Input Pullup LVCMOS/LVTTL interface levels. Output enable pin for Bank B outputs. See Table 4B. 12 OEB Input Pullup LVCMOS/LVTTL interface levels. Output select pin. When LOW, selects LVDS levels. When HIGH, selects 13 SEL OUT Input Pullup LVPECL levels. LVCMOS/LVTTL interface levels. See Table 1B. Power Power supply pin. See Table 1A. 14 V CC TAP 15, 16 nQB1, QB1 Output Differential output pair. LVPECL or LVDS interface levels. 17, 18 nQB0, QB0 Output Differential output pair. LVPECL or LVDS interface levels. 19, 20 nQA1, QA1 Output Differential output pair. LVPECL or LVDS interface levels. 21, 22 nQA0, QA0 Output Differential output pair. LVPECL or LVDS interface levels. Power Negative supply pin. 23 V EE Power Power supply pin. 24 V CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 3. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup/Pulldown Resistor 50 k VCC/2 ICS859S0424BGI REVISION A OCTOBER 12, 2011 2 2011 Integrated Device Technology, Inc.