VEE ICS859S0412I 4:2, Differential-to-LVPECL/LVDS Clock Multiplexer DATA SHEET General Description Features The ICS859S0412I is a 4:2 Differential-to-LVPECL/ LVDS Clock High speed 4:1 differential multiplexer with a 1:2 fanout buffer Multiplexer which can operate up to 3GHz. The ICS859S0412I has 4 Two differential LVPECL or LVDS output pairs selectable differential PCLKx/nPCLKx clock inputs. The PCLKx, Four selectable differential PCLKx, nPCLKx input pairs nPCLKx input pairs can accept LVPECL, LVDS, CML or levels. The PCLKx, nPCLKx pairs can accept the following differential fully differential architecture and low propagation delay make it ideal input levels: LVPECL, LVDS, CML for use in clock distribution circuits. Maximum output frequency: 3GHz Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input Part-to-part skew: 100ps (maximum) Propagation delay: 565ps (typical) at 3.3V Additive phase jitter, RMS: 0.22ps (typical) at 3.3V Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup OE CLK SEL1 1 20 CLK SEL0 Pulldown PCLK0 2 19 VCC CLK SEL0 nPCLK0 3 18 VEE Pulldown CLK SEL1 PCLK1 4 17 Q0 nPCLK1 5 16 nQ0 PCLK2 6 15 Q1 Pulldown PCLK0 nPCLK2 7 14 nQ1 Pullup/Pulldown 0 0 nPCLK0 PCLK3 8 13 nPCLK3 9 12 VCC TAP Pulldown Q0 PCLK1 OE 10 11 SEL OUT Pullup/Pulldown 0 1 nPCLK1 nQ0 ICS859S0412I Q1 Pulldown PCLK2 20-Lead TSSOP 1 0 Pullup/Pulldown nPCLK2 nQ1 6.5mm x 4.4mm x 0.925mm package body Pulldown G Package PCLK3 1 1 Pullup/Pulldown nPCLK3 Top View Pullup SEL OUT ICS859S0412BGI REVISION A MAY 23, 2012 1 2012 Integrated Device Technology, Inc.ICS859S0412I Data Sheet 4:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1, CLK SEL1, Input Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels. 20 CLK SEL0 2 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 3 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 4 PCLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 5 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 6 PCLK2 Input Pulldown Non-inverting differential clock input. Pullup/ 7 nPCLK2 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 8 PCLK3 Input Pulldown Non-inverting differential clock input. Pullup/ 9 nPCLK3 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 10 OE Input Pullup Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels. Output select pin. When LOW, selects LVDS levels. When HIGH, selects LVPECL 11 SEL OUT Input Pullup levels. LVCMOS/LVTTL interface levels. See Table 3B. 12 V Power Positive supply pin. See Table 3A. CC TAP 13, 18 V Power Negative supply pins. EE 14, 15 nQ1, Q1 Output Differential output pair. LVPECL or LVDS interface levels. 16, 17 nQ0, Q0 Output Differential output pair. LVPECL or LVDS interface levels. 19 V Power Positive supply pin. CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup/Pulldown Resistor 75 k VCC/2 ICS859S0412BGI REVISION A MAY 23, 2012 2 2012 Integrated Device Technology, Inc.