GND LVCMOS/LVTTL Clock Divider ICS87001I-01 DATA SHEET General Description Features The ICS87001I-01 is a low skew, 1, 2, 3, 4, 5, 6, 8, 16 One LVCMOS / LVTTL output LVCMOS/LVTTL Clock Divider. The ICS87001I-01 has selectable Selectable LVCMOS / LVTTL clock inputs clock inputs that accept single ended input levels. Output enable pin Maximum output frequency: 250MHz controls whether the output is in the active or high impedance state. Part-to-part skew: 135ps (typical) The ICS87001I-01 is characterized at 3.3V, 2.5V and mixed Power supply modes: 3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating Core/Output modes.Guaranteed part-to-part skew characteristics make the 3.3V/3.3V ICS87001I-01 ideal for those applications demanding well defined 3.3V/2.5V performance and repeatability. 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown CLK SEL VDDO OE 1 16 N Output Divider 15 2 nc VDD N2:N0 CLK0 14 Q 3 0 0 0 1 (default) Pulldown CLK0 13 CLK SEL nc 4 0 001 2 12 CLK1 GND 5 010 3 11 Q N2 6 nc 011 4 10 Pulldown N1 7 nc CLK1 1 100 5 9 N0 8 101 6 110 8 ICS87001I-01 111 16 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body 3 Pulldown N2:N0 G Package Top View Pullup OE ICS87001BGI-01 REVISION A JANUARY 23, 2013 1 2013 Integrated Device Technology, Inc.ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER Table 1. Pin Descriptions Number Name Type Description Output enable. When LOW, output is in HIGH impedance state. 1 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Power Power supply pin. 2V DD 3, 5 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Input clock selection. When HIGH, selects CLK1 input. 4 CLK SEL Input Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 6, 7, 8 N2, N1, N0 Input Pulldown Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3. 9, 12 GND Power Power supply ground. 10, 11, 13, 15 nc Unused No connect. 14 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. Power Output supply pin. 16 V DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 6 pF DDO Power Dissipation C = 2.625V 5 pF V PD DDO Capacitance = 1.95V 5 pF V DDO V = 3.3V5% 17 DDO Output Impedance V = 2.5V5% 20 R OUT DDO V = 1.8V0.15V 28 DDO Function Table Table 3. Programmable Output Divider FunctionTable Inputs N2 N1 N0 N DividerValue Maximum Output Frequency (MHz) 0 0 0 1 (default) 250 0 0 1 2 125 0 1 0 3 83.333 0 1 1 4 62.5 1 0 0 5 50 1 0 1 6 41.667 1 1 0 8 31.25 1 1 1 16 15.625 ICS87001BGI-01 REVISION A JANUARY 23, 2013 2 2013 Integrated Device Technology, Inc.