ICS87008I LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) Generator. The device has 2 banks of 4 outputs and each Selectable differential CLK1, nCLK1 or bank can be independently selected for 1 or 2 frequency LVCMOS clock input operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage CLK1, nCLK1 pair can accept the following differential levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/ input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL LVTTL outputs are designed to drive 50 series or parallel CLK0 supports the following input types: terminated transmission lines. LVCMOS, LVTTL The divide select inputs, DIV SELA and DIV SELB, control the Maximum output frequency: 250MHz output frequency of each bank. The output banks can be independently selected for 1 or 2 operation. The bank enable Independent bank control for 1 or 2 operation inputs, CLK ENA and CLK ENB, support enabling and disabling Glitchless, asynchronous clock enable/disable each bank of outputs individually. The CLK ENA and CLK ENB circuitry has a synchronizer to prevent runt pulses when Output skew: 105ps (maximum) 3.3V core/3.3V output enabling or disabling the clock outputs. The master reset Bank skew: 70ps (maximum) 3.3V core/3.3V output input, nMR/OE, resets the 1/2 flip flops and also controls the active and high impedance states of all outputs. This pin has 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating an internal pull-up resistor and is normally used only for test supply purposes or in systems which use low power modes. -40C to 85C ambient operating temperature The ICS87008I is characterized to operate with the core at 3.3V Available in both standard and lead-free RoHS compliant or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, packages output, and part-to-part skew characteristics make the 87008I ideal for those clock applications demanding well-defined performance and repeatability. BLOCK DIAGRAM PIN ASSIGNMENT nMR/OE CLK1 1 24 CLK0 DIV SELA nCLK1 CLK SEL 2 23 VDDOA 3 VDDOB 22 CLK1 QA0 4 21 QB0 1 1 1 nCLK1 QA1 5 20 QB1 4 QA0:QA3 2 CLK0 0 GND 6 19 GND 0 LE QA2 7 QB2 18 CLK ENA QA3 8 17 QB3 D VDDOA 9 16 VDDOB DIV SELA DIV SELB 10 15 CLK SEL CLK ENA 11 14 CLK ENB 1 VDD 13 nMR/OE 12 4 QB0:QB3 0 LE ICS87008I CLK ENB D 24-Lead TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package DIV SELB Top View 87008AGI www.idt.com REV. B JULY 31, 2010 1ICS87008I LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 11CtLKInnpuP.ulldow Non-inverting differential clock input Pullup/ 21ntCLK Inpu Inverting differential clock input. V /2 default when left floating. DD Pulldown 3V, 9 P.ower Output Bank A supply pins DDOA QA0, QA1, 4, 5, 7, 8O.utput Bank A outputs. LVCMOS / LVTTL interface levels QA2, QA3 6D, 19 GrNP.owe Supply ground Controls frequency division for Bank A outputs. 1A0 DtIV SELIpnpu Pullu LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. 1A1 CtLK ENIpnpu Pullu If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. 1V2 P.ower Power supply pin DD Master reset. When LOW, resets the 1/2 flip flops and sets the 1E3 ntMR/OIpnpu Pullu outputs to high impedance. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. Active HIGH. 1B4 CtLK ENIpnpu Pullu If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. 1B5 DtIV SELIpnpu Pullu LVCMOS / LVTTL interface levels.. 1V6, 22P.ower Output Bank B supply pins DDOB QB3, QB2, 17, 18, 20, 21O.utput Bank B outputs. LVCMOS / LVTTL interface levels QB1, QB0 Clock select input. When HIGH, selects CLK1, nCLK1 inputs. 2L3 CtLK SEInnpu Pulldow When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 204 CtLKInnpuP.ulldow LVCMOS / LVTTL clock input NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Units SrymbolPsaramete Tmest Condition MlinimuTmypica Maximu C Input Capacitance 4Fp IN R Input Pullup Resistor 5k1 PULLUP R Input Pulldown Resistor 5k1 PULLDOWN V , V=83.465V NOTE 1 1Fp DD DDOx V , V=02.625V NOTE 1 2Fp DD DDOx Power Dissipation C V = 3.465, V=02.625V NOTE 1 2Fp PD DD DDOx Capacitance (per output) V = 3.465, V=01.89V NOTE 1 3Fp DD DDOx V = 2.625, V=01.89V NOTE 1 2Fp DD DDOx R Output Impedance 7 OUT NVOTE 1: denotes V and V . DDOx DADO DBDO TABLE 3. FUNCTION TABLE Isnputs Output nxMR/OECxLK ENDXIV SELByank Qx Frequenc 0X X HAiZ N/ 11 0 A2ctive fIN/ 11 1 ANctive fI 10 X LAow N/ 87008AGI www.idt.com REV. B JULY 31, 2010 2