Low Skew, 1-to-16 87016I LVCMOS/LVTTL Clock Generator DATASHEET Description Features The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) The device has four banks of four outputs and each bank can be Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input independently selected for 1 or 2 frequency operation. Each bank CLK1, CLK1 pair can accept the following differential also has its own power supply pins so that the banks can operate at input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low CLK0 supports the following input types: LVCMOS, LVTTL impedance LVCMOS/LVTTL outputs are designed to drive 50 Maximum output frequency: 250MHz series or parallel terminated transmission lines. Independent bank control for 1 or 2 operation The divide select inputs, DIV SELA:DIV SELD, control the output frequency of each bank. The output banks can be independently Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V selected for 1 or 2 operation. The bank enable inputs, operation CLK ENA:CLK END, support enabling and disabling each bank of Asynchronous clock enable/disable outputs individually. The CLK ENA:CLK END circuitry has a Output skew: 170ps (maximum) synchronizer to prevent runt pulses when enabling or disabling the Bank skew: 50ps (maximum clock outputs. The master reset input, MR/OE, resets the 1/2 flip flops and also controls the active and high impedance states of all Part-to-Part Skew: 800ps (maximum) outputs. This pin has an internal pull-up resistor and is normally used Supply modes: only for test purposes or in systems which use low power modes. Core/Output 3.3V/3.3V The 87016I is characterized to operate with the core at 3.3V or 2.5V 3.3V/2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and 3.3V/1.8V part-to-part skew characteristics make the 87016I ideal for those 2.5V/2.5V 2.5V/1.8V clock applications demanding well-defined performance and repeatability. -40C to 85C ambient operating temperature Lead-free packaging Block Diagram Pin Assignment MR/OE D CLK0 4 1 LE 0 1 QA0:QA3 48 47 46 45 44 43 42 41 40 39 38 37 2 0 1 CLK1 VDD GND 1 36 CLK1 D CLK0 2 35 QB0 4 LE 1 QB0:QB3 DIV SELA 3 34 VDDOB CLK SEL DIV SELB 4 33 QB1 0 DIV SELC 5 32 GND DIV SELA D DIV SELD 6 31 QB2 LE 4 1 DIV SELB QC0:QC3 CLK ENA 7 30 VDDOB CLK ENB 8 29 QB3 DIV SELC 0 CLK ENC 9 28 GND D DIV SELD CLK END 10 QC0 27 4 LE 1 QD0:QD3 MR/OE 11 26 VDDOC CLK ENA GND 0 12 25 QC1 13 14 15 16 17 18 19 20 21 22 23 24 CLK ENB CLK ENC CLK END 87016I 48-LQFP 7 7 1.4 mm package body Y Package Top View January 22, 2020 1 2020 Renesas Electronics Corporation QD3 VDD VDDOD CLK1 QD2 CLK1 GND CLK SEL QD1 GND VDDOD QA0 QD0 VDDOA GND QA1 QC3 GND VDDOC QA2 QC2 VDDOA GND QA387016I DATASHEET Table 1. Pin Descriptions Number Name Type Description 1, 48 V Power Positive supply pins. DD 2 CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Controls frequency division for Bank A outputs. See Table 3. 3 DIV SELA Input Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. See Table 3. 4 DIV SELB Input Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. See Table 3. 5 DIV SELC Input Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. See Table 3. 6 DIV SELD Input Pullup LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive 7 CLK ENA Input Pullup low. LVCMOS/LVTTL interface levels. See Table 3. Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive 8 CLK ENB Input Pullup low. LVCMOS/LVTTL interface levels. See Table 3. Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive 9 CLK ENC Input Pullup low. LVCMOS/LVTTL interface levels. See Table 3. Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive 10 CLK END Input Pullup low. LVCMOS/LVTTL interface levels. See Table 3. Master reset. When LOW, resets the 1/2 flip flops and sets the outputs to 11 MR/OE Input Pullup high impedance. LVCMOS / LVTTL interface levels. 12, 16, 20, 24, 28, 32, GND Power Power supply ground 36, 40, 44 QD3, QD2, 13, 15, 17, 19 Output Bank D single-ended clock outputs. LVCMOS/LVTTL interface levels. QD1, QD0 14, 18 V Power Bank D output supply pins. DDOD QC3, QC2, 21, 23, 25, 27 Output Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels. QC1, QC0 22, 26 V Power Bank C output supply pins. DDOC QB3, QB2, 29, 31, 33, 35 Output Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels. QB1, QB0 30, 34 V Power Bank B output supply pins. DDOB QA3, QA2, 37, 39, 41, 43 Output Bank A single-ended clock outputs. LVCMOS/LVTTL interface levels. QA1, QA0 38, 42 V Power Bank B output supply pins. DDOA Clock select input. When HIGH, selects CLK1, CLK1 inputs. 45 CLK SEL Input Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 46 CLK1 Input Pullup Inverting differential clock input. 47 CLK1 Input Pulldown Non-inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. January 22, 2020 2 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR