Low Skew, 1-to-16 87016 LVCMOS/LVTTL Clock Generator DATASHEET GENERAL DESCRIPTION FEATURES The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) The device has 4 banks of 4 outputs and each bank can be Selectable differential CLK1, nCLK1 or independently selected for 1 or 2 frequency operation. Each LVCMOS clock input bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and CLK1, nCLK1 pair can accept the following differential input 1.8V. The low impedance LVCMOS/LVTTL outputs are designed levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL to drive 50 series or parallel terminated transmission lines. CLK0 supports the following input types: The divide select inputs, DIV SELA:DIV SELD, control the LVCMOS, LVTTL output frequency of each bank. The output banks can be Maximum output frequency: 250MHz independently selected for 1 or 2 operation. The bank enable inputs, CLK ENA:CLK END, support enabling and disabling Independent bank control for 1 or 2 operation each bank of outputs individually. The CLK ENA:CLK END Independent output bank voltage settings for 3.3V, 2.5V, circuitry has a synchronizer to prevent runt pulses when or 1.8V operation enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the 1/2 ip ops and also controls the Asynchronous clock enable/disable active and high impedance states of all outputs. This pin has Output skew: 170ps (maximum) an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. Bank skew: 30ps (maximum) The 87016 is characterized to operate with the core at Part-to-part skew: 750ps (maximum) 3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply bank, output, and part-to-part skew characteristics make the 87016 ideal for those clock applications demanding 0C to 85C ambient operating temperature well-de ned performance and repeatability. Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 48-Pin LQFP 7mm x 7mm x 1.4mm body package Y Package Top View . 01/21/20 1 20tegrated Device Technology, Inc.87016 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 48 V Power Positive supply pins. DD 2 CLK0 Input Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank A outputs. 3 DIV SELA Input Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs 4 DIV SELB Input Pullup LVCMOS / LVTTL interface levels.. Controls frequency division for Bank C outputs. 5 DIV SELC Input Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. 6 DIV SELD Input Pullup LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. 7 CLK ENA Input Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. Active HIGH. 8 CLK ENB Input Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank C outputs. Active HIGH. 9 CLK ENC Input Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank D outputs. Active HIGH. 10 CLK END Input Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Master reset. When LOW, resets the 1/2 ip ops and sets the 11 nMR/OE Input Pullup outputs to high impedance. LVCMOS / LVTTL interface levels. 12, 16, 20, 24, 28, GND Power Power supply ground. 32, 36, 40, 44 QD3, QD2, 13, 15, 17, 19 Output Bank D outputs. LVCMOS / LVTTL interface levels. QD1, QD0 14, 18 V Power Output Bank D power supply pins. DDOD QC3, QC2, 21, 23, 25, 27 Output Bank C outputs. LVCMOS / LVTTL interface levels. QC1, QC0 22, 26 V Power Output Bank C power supply pins. DDOC QB3, QB2, 29, 31, 33, 35 Output Bank B outputs. LVCMOS / LVTTL interface levels. QB1, QB0 30, 34 V Power Output Bank B power supply pins. DDOB QA3, QA2, 37, 39, 41, 43 Output Bank A outputs. LVCMOS / LVTTL interface levels. QA1, QA0 38, 42 V Power Output Bank A power supply pins. DDOA Clock select input. When HIGH, selects CLK1, nCLK1 inputs. 45 CLK SEL Input Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 46 nCLK1 Input Pullup Inverting differential clock input. 47 CLK1 Input Pulldown Non-inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. LOW SKEW, 1-TO-16 2 REVISION C 06/26/15 LVCMOS/LVTTL CLOCK GENERATOR