Q6 VDDO GND Q1 Q7 GND VDDO Q0 SEL VDDO VDDA 2 PLL SEL FB IN VDD VDD ICS8705 Zero Delay, Differential-to-LVCMOS/ NRND LVTTL Clock Generator NOT RECOMMENDED FOR NEW DESIGNS GENERAL DESCRIPTION FEATURES The ICS8705 is a highly versatile 1:8 Differential-to-LVCMOS/ 8 LVCMOS/LVTTL outputs, 7 typical output impedance LVTTL Clock Generator. The ICS8705 has two selectable clock Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs inputs. The CLK1, nCLK1 pair can accept most standard dif- CLK1, nCLK1 pair can accept the following differential ferential input levels. The single ended CLK0 input accepts input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL LVCMOS or LVTTL input levels.The ICS8705 has a fully inte- CLK0 input accepts LVCMOS or LVTTL input levels grated PLL and can be configured as zero delay buffer, mul- tiplier or divider and has an input and output frequency range Output frequency range: 15.625MHz to 250MHz of 15.625MHz to 250MHz. The reference divider, feedback Input frequency range: 15.625MHz to 250MHz divider and output divider are each programmable, thereby VCO range: 250MHz to 500MHz allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows External feedback for zero delay clock regeneration with configurable frequencies the device to achieve zero delay between the input clock and the output clocks. The PLL SEL pin can be used to by- Programmable dividers allow for the following output-to- pass the PLL for system test and debug purposes. In bypass input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 mode, the reference clock is routed around the PLL and into Fully integrated PLL the internal output dividers. Cycle-to-cycle jitter: 45ps (maximum) Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum) Static Phase Offset: 25 125ps (maximum), CLK0 Full 3.3V or 2.5V operating supply 0C to 70C ambient operating temperature Lead-Free package fully RoHS compliant Not Recommended for New Designs. For new designs, contact IDT. BLOCK DIAGRAM PIN ASSIGNMENT PLL SEL Q0 2, 4, 8, 16, 32 ,64, 128 0 Q1 CLK0 0 32 31 30 29 28 27 26 25 Q2 1 SEL0 1 VDDO 24 CLK1 1 PLL Q3 SEL1 2 Q5 nCLK1 23 CLK0 3 GND 22 CLK SEL Q4 nc 4 Q4 8:1, 4:1, 2:1, 1:1, 21 FB IN ICS8705 1:2, 1:4, 1:8 CLK1 5 VDDO 20 Q5 nCLK1 6 Q3 19 Q6 CLK SEL 7 GND 18 MR 8 Q2 17 Q7 9 10 11 12 13 14 15 16 SEL0 SEL1 SEL2 32-Lead LQFP 7mm x 7mm x 1.4 mm SEL3 Y Package Top View MR 8705BY REV. H MAY 30, 2013 1ICS8705 Zero Delay, Differential-to-LVCMOS/ NRND LVTTL Clock Generator TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio SEL0, SEL1, Determines output divider values in Table 3. 1, 2, 11 Innput Pulldow SEL2 LVCMOS/LVTTL interface levels. 30CtLK InnpuP.ulldow Clock input. LVCMOS/LVTTL interface levels 4cn.No connect 51CtLKInnpuP.ulldow Non-inverting differential clock input 61ntCLK IpnpuP.ullu Inverting differential clock input Clock select input. When HIGH, selects differential CLK1, nCLK1. 7LCtLK SEInnpu Pulldow When LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 8RMtInnpu Pulldow reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 9V, 32 P.ower Core supply pins DD LVCMOS/LVTTL feedback input to phase detector for regenerating 1N0 FtB I Innpu Pulldow clocks withzero dela. Connect to one of the outputs. LVCMOS/LVTTL interface levels. 12, 16, 20, VP.ower Output supply pins DDO 24, 28 13, 15, 17, Q0, Q1, Q2, Clock output. 7 typical output impedance. 19, 21, 23, Q3, Q4, Q5, Output LVCMOS/LVTTL interface levels. 25, 27 Q6, Q7 1D4, 18, 22, 26GrNP.owe Power supply ground Determines output divider values in Table 3. 239 StEL Innpu Pulldow LVCMOS/LVTTL interface levels. 3V0 P.ower Analog supply pin DDA Selects between the PLL and reference clock as input to the dividers. 3L1 PtLL SEIpnpu Pullu When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN R Input Pullup Resistor 5K1 PULLUP R Input Pulldown Resistor 5K1 PULLDOWN C Power Dissipation Capacitance PD V ,V ,V=33.465V 2Fp DD DDO DDA (per output) R Output Impedance 7 OUT 8705BY REV. H MAY 30, 2013 2