FemtoClock Zero Delay Buffer/ Clock ICS8714004I Generator for PCI Express and Ethernet DATA SHEET General Description Features The ICS8714004I is Zero-Delay Buffer/Frequency Multiplier with four Four 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for zero delay clock One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, regeneration. In PCI Express and Ethernet applications, 100MHz LVHSTL, HCSL and 125MHz are the most commonly used reference clock frequencies and each of the four output pairs can be independently One M-LVDS I/O pair (MLVDS, nMLVDS) set for either 100MHz or 125MHz. With an output frequency range of Output frequency range: 98MHz - 165MHz 98MHz to 165MHz, the device is also suitable for use in a variety of Input frequency range: 19.6MHz - 165MHz other applications such as Fibre Channel (106.25MHz) and XAUI VCO range: 490MHz - 660MHz (156.25MHz). The M-LVDS Input/Output pair is useful in backplane applications when the reference clock can either be local (on the PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter compliant same board as the ICS8714004I) or remote via a backplane connector. In output mode, an input from a local reference clock External feedback for zero delay clock regeneration applied to the CLK, nCLK input pins is translated to M-LVDS and RMS phase jitter 125MHz (1.875MHz 20MHz): driven out to the MLVDS, nMLVDS pins. In input mode, the internal 0.558ps (typical) M-LVDS driver is placed in a High-Impedance state using the Full 3.3V supply mode OE MLVDS pin and MLVDS, nMLVDS pin then becomes an input -40C to 85C ambient operating temperature (e.g. from a backplane). Lead-free (RoHs 6) packaging The ICS8714004I uses low phase noise FemtoClock technology, thus making it ideal for such applications as PCI Express Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel, and 10 Gigabit Ethernet. It is packaged in a 40-VFQFN package (6mm x 6mm). Pin Assignment 40 39 38 37 36 35 34 33 32 31 VDD 1 30 VDD OE MLVDS 2 29 Q2 3 MLVDS 28 nQ2 4 nMLVDS 27 GND 5 PLL SEL 26 Q3 FBO DIV 6 25 nQ3 MR 7 24 FBOUT OE0 8 23 nFBOUT OE1 9 22 VDD 10 GND 21 IREF 11 12 13 14 15 16 17 18 19 20 ICS8714004I 40-Lead VFQFN 6mm x 6mm x 0.925mm package body 4.65mm x 4.65mm Epad Size K Package Top View ICS8714004DKI REVISION A MARCH 24, 2014 1 2014 Integrated Device Technology, Inc. VDD PDIV1 FBI DIV0 PDIV0 FBI DIV1 nCLK nFBIN CLK FBIN VDDA GND VDD QDIV0 Q0 QDIV1 nQ0 Q1 QDIV2 QDIV3 nQ1 ICS8714004I Data Sheet FemtoCLock Zero Delay Buffer/Clock Generator for PCI Express and Ethernet Block Diagram 2 OE 1:0 (PU, PU) Pulldown QDIV0 (PD) PDIV1 Pulldown PDIV0 Q0 QDIV0 0 4 (default) PDIV1:0 Pulldown 1 5 CLK nQ0 00 4 (default) 01 5 Pullup/Pulldown nCLK QDIV1 (PD) 10 8 11 1 Q1 QDIV1 Pullup OE MLVDS 0 4 (default) 1 5 0 nQ1 MLVDS QDIV2 (PD) nMLVDS Q2 PLL QDIV2 PD 0 4 (default) VCO Range 1 Pullup 1 5 490-660MHz nQ2 FBI DIV1 Pullup FBI DIV0 QDIV3 (PD) Q3 Pulldown QDIV3 FBIN FBI DIV1:0 0 4 (default) 00 1 Pullup/Pulldown 1 5 01 2 nFBIN nQ3 10 4 11 5 (default) IREF FBO DIV (PD) FBOUT FBO DIV Pullup PLL SEL 0 4 (default) 1 5 nFBOUT Pulldown MR Pull-up resistor (PU) on pin (power-up default is HIGH if not externally driven) Pull-down resistor (PD) on pin (power-up default is LOW if not externally driven) ICS8714004DKI REVISION A MARCH 24, 2014 2 2014 Integrated Device Technology, Inc.