Differential-to-HSTL Zero Delay Clock ICS8725B-01 Generator DATA SHEET General Description Features The ICS8725B-01 is a highly versatile 1:5 Differential- Five differential HSTL output pairs ICS to-HSTL clock generator and a member of the Selectable differential CLKx/nCLKx input pairs HiPerClockS HiPerClockS family of High Performance Clock CLKx/nCLKx pairs can accept the following differential Solutions from IDT. The ICS8725B-01 has a fully input levels: LVPECL, LVDS, HSTL, HCSL, SSTL integrated PLL and can be configured as zero delay Output frequency range: 31.25MHz to 700MHz buffer, multiplier or divider, and has an output frequency range of Input frequency range: 31.25MHz to 700MHz 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the VCO range: 250MHz to 700MHz following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, External feedback for zero delay clock regeneration 1:8. The external feedback allows the device to achieve zero delay with configurable frequencies between the input clock and the output clocks. The PLL SEL pin can Programmable dividers allow for the following output-to-input be used to bypass the PLL for system test and debug purposes. In frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 bypass mode, the reference clock is routed around the PLL and into Static phase offset: 15ps 135ps the internal output dividers. Cycle-to-cycle jitter: 25ps (maximum) Output skew: 45ps (maximum) 3.3V core, 1.8V output operating supply 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram Pin Assignment PLL SEL Q0 nQ0 Q1 nQ1 32 31 30 29 28 27 26 25 1, 2, 4, 8 0 16, 32, 64 CLK0 SEL0 1 VDDO Q2 24 0 nCLK0 nQ2 SEL1 2 23 Q3 1 CLK1 Q3 1 CLK0 3 22 nQ3 nCLK1 nQ3 Q2 nCLK0 4 21 PLL Q4 CLK SEL CLK1 nQ2 nQ4 5 20 nCLK1 6 19 Q1 8:1, 4:1, 2:1, 1:1 FB IN 1:2, 1:4, 1:8 CLK SEL 7 nQ1 nFB IN 18 MR 8 VDDO 17 9 10 11 12 13 14 15 16 SEL0 SEL1 ICS8725B-01 SEL2 32-Lead LQFP SEL3 7mm x 7mm x 1.4mm package body Y Package MR Top View ICS8725BY-01 REVISION A JULY 16, 2009 1 2009 Integrated Device Technology, Inc. VDD VDD nFB IN PLL SEL FB IN VDDA SEL2 SEL3 GND GND nQ0 Q4 Q0 nQ4 VDDO VDDOICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1, 2, SEL0, SEL1, Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 12, 29 SEL2, SEL3 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0, 7 CLK SEL Input Pulldown nCLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 8 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Power Core supply pins. 9, 32 V DD Inverting differential feedback input to phase detector for regenerating clocks with 10 nFB IN Input Pullup Zero Delay. Non-inverted differential feedback input to phase detector for regenerating clocks 11 FB IN Input Pulldown with Zero Delay. 13, 28 GND Power Power supply ground. 14, 15 nQ0, Q0 Output Differential output pair. HSTL interface levels. 16, 17, 24, V Power Output supply pins. DDO 25 18, 19 nQ1, Q1 Output Differential output pair. HSTL interface levels. 20, 21 nQ2, Q2 Output Differential output pair. HSTL interface levels. 22, 23 nQ3, Q3 Output Differential output pair. HSTL interface levels. 26, 27 nQ4, Q4 Output Differential output pair. HSTL interface levels. Power Analog supply pin. 30 V DDA PLL select. Selects between the PLL and reference clock as the input to the 31 PLL SEL Input Pullup dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 2pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS8725BY-01 REVISION A JULY 16, 2009 2 2009 Integrated Device Technology, Inc.