Low Skew, 2/4,4/5/6, 87339I-11 Data Sheet Differential-to-3.3V LVPECL Clock Generator GENERAL DESCRIPTION FEATURES The 87339I-11 is a low skew, high performance Dual 2, 4 differential 3.3V LVPECL outputs Differential-to-3.3V LVPECL Clock Generator/Divider. The Dual 4, 5, 6 differential 3.3V LVPECL outputs 87339I-11 has one differential clock input pair. The CLK, One differential CLK, nCLK input pair nCLK pair can accept most standard differential input levels. The clock enable isinternally synchronized to CLK, nCLK pair can accept the following differential eliminate runt pulses on theoutputs during asynchronous as- input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL sertion/deassertion of the clock enable pin. Maximum clock input frequency: 1GHz Guaranteed output and part-to-part skew charac- Translates any single ended input signal (LVCMOS, LVTTL, teristics make the 87339I-11 ideal for clock distribution GTL) to LVPECL levels with resistor bias on nCLK input applications demanding well defined performance and repeatability. Output skew: 35ps (maximum) Part-to-part skew: 385ps (maximum) Bank skew: Bank A - 20ps (maximum) Bank B - 20ps (maximum) Propagation delay: 2.1ns (maximum) LVPECL mode operating voltage supply range: V = 3V to 3.6V, V = 0V CC EE Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 87339I-11 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View 20-Lead SOIC, 300MIL 7.5mm x 12.8mm x 2.25mm package body M Package Top View 2016 Integrated Device Technology, Inc 1 Revision B January 25, 201687339I-11 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 8, 20 V Power Positive supply pins. CC 2 nCLK EN Input Pulldown Clock enable. LVCMOS / LVTTL interface levels. See Table 3. Selects divide value for Bank B outputs as described in Table 3. 3 DIV SELB0 Input Pulldown LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 RESERVED Reserve Reserve pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go 7 MR Input Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects divide value for Bank B outputs as described in Table 3. 9 DIV SELB1 Input Pulldown LVCMOS / LVTTL interface levels. Selects divide value for Bank A outputs as described in Table 3. 10 DIV SELA Input Pulldown LVCMOS / LVTTL interface levels. 11 V Power Negative supply pin. EE 12, 13 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 18, 19 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision B January 25, 2016