4/5 Differential-to-3.3V LVPECL 87354 Clock Generator DATASHEET GENERAL DESCRIPTION FEATURES The 87354 is a high performance 4/5 One differential 3.3V LVPECL output Differential-to-3.3V LVPECL Clock Generator. The CLK, nCLK pair can ac- One CLK, nCLK input pair cept most standard differential input levels.The 87354 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew CLK, nCLK pair can accept the following differential characteristics make the 87354 ideal for those clock input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL distribution applications demanding well defined Maximum clock input frequency: 1GHz performance and repeatability. Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input Part-to-part skew: 300ps (maximum) Propagation delay: 2.1ns (maximum) LVPECL mode operating voltage supply range: V = 3.0V to 3.465V, V = 0V CC EE -40C to 85C ambient operating temperature Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT CLK 1 8 Vcc 4 0 Q CLK nCLK Q 2 7 nQ nCLK MR 3 6 nQ 5 1 R F SEL 4 5 VEE 87354 MR 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package F SEL Top View 87354 REVISION A 2/12/15 1 2015 Integrated Device Technology, Inc.87354 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output (Q) to go low and the inverted output (nQ) 3 MR Input Pulldown to go high. When logic LOW, the internal dividers and the output are enabled. LVCMOS / LVTTL interface levels. See Table 3. Selects divider value for Q, nQ outputs as described in Table 3. 4 F SEL Input Pulldown LVCMOS / LVTTL interface levels. 5V Power Negative supply pin. EE 6, 7 nQ, Q Output Differential output pair. LVPECL interface levels. 8V Power Positive supply pin. CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN TABLE 3. FUNCTION TABLE MR F SEL Divide Value 1 X Reset: Q output low, nQ output high 00 4 01 5 CLK MR Q FIGURE 1. TIMING DIAGRAM 4/5 DIFFERENTIAL-TO- 2 REVISION A 2/12/15 3.3V LVPECL CLOCK GENERATOR