1:5, Differential-to-3.3V LVPECL Zero 8735-31 Delay Clock Generator Data Sheet General Description Features The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL Five differential 3.3V LVPECL output pairs Clock Generator. The 8735-31 has a fully integrated PLL and can Selectable differential clock inputs be configured as zero delay buffer, multiplier or divider, and has an CLKx/nCLKx pairs can accept the following differential output frequency range of 15.625MHz to 350MHz. The reference input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL divider, feedback divider and output divider are each Output frequency range: 15.625MHz to 350MHz programmable, thereby allowing for the following output-to-input Input frequency range: 15.625MHz to 350MHz frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve zero delay between the VCO range: 250MHz to 700MHz input clock and the output clocks. The PLL SEL pin can be used External feedback for zero delay clock regeneration to bypass the PLL for system test and debug purposes. In bypass with configurable frequencies mode, the reference clock is routed around the PLL and into the Programmable dividers allow for the following output-to-input internal output dividers. frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Cycle-to-cycle jitter: 60ps (maximum) Output skew: 35ps (maximum) Static phase offset: 55ps 125ps Full 3.3V supply voltage 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Q0 nQ0 Pullup PLL SEL Q1 2, 4, 8, 16, nQ1 32 31 30 29 28 27 26 25 0 32, 64, 128 Q2 SEL0 1 24 VCCO Pulldown CLK0 Pullup 0 nQ2 nCLK0 2 Q3 SEL1 23 1 Q3 Pulldown CLK1 3 nQ3 CLK0 22 1 Pullup nQ3 nCLK1 Q4 nCLK0 4 21 Q2 PLL nQ4 Pulldown CLK SEL CLK1 5 20 nQ2 8:1, 4:1, 2:1, 1:1, nCLK1 6 Q1 19 Pulldown FB IN 1:2, 1:4, 1:8 Pullup CLK SEL 7 nQ1 nFB IN 18 MR 8 17 VCCO 9 10 11 12 13 14 15 16 Pulldown SEL0 Pulldown SEL1 8735-31 Pulldown SEL2 32-Lead LQFP 7mm x 7mm x 1.4mm package body Pulldown SEL3 Y Package Pulldown MR Top View 2016 Integrated Device Technology, Inc 1 Revision B January 27, 2016 VCC VCC nFB IN PLL SEL FB IN VCCA SEL2 SEL3 VEE VEE nQ0 Q4 nQ4 Q0 VCCO VCCO8735-31 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2, SEL0, SEL1, Determines output divider values in Table 3. Input Pulldown 12, 29 SEL2, SEL3 LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. Clock select input. When HIGH, selects CLK1/nCLK1. When LOW, selects 7 CLK SEL Input Pulldown CLK0/nCLK0. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 8 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Power Core supply pins. 9, 32 V CC Inverting differential feedback input to phase detector for regenerating clocks 10 nFB IN Input Pullup with zero delay. Non-inverted differential feedback input to phase detector for regenerating 11 FB IN Input Pulldown clocks with zero delay. Power Negative supply pins. 13, 28 V EE 14, 15 nQ0, Q0 Output Differential output pair. LVPECL interface levels. Power Output supply pins. 16, 17, 24, 25 V CCO 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 20, 21 nQ2, Q2 Output Differential output pair. LVPECL interface levels.. 22, 23 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 26, 27 nQ4, Q4 Output Differential output pair. LVPECL interface levels. Power Analog supply pin. 30 V CCA PLL select. Selects between the PLL and reference clock as the input to the 31 PLL SEL Input Pullup dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision B January 27, 2016